Intel 820E Manuale Utente
Intel
®
820E Chipset
R
Design Guide
127
Table 31. Interrupt Interface
Checklist Items
Recommendations
Reason/Effect
PIRQ#[D:A]
These signals require a pull-up
resistor. A 2.7 k
resistor. A 2.7 k
Ω
pull-up resistor
to V
CC
5 V or an 8.2 k
Ω
pull-up
resistor to V
CC
3.3 V is
recommended.
In a non-APIC mode, the PIRQx# signals can be
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or
15. Each PIRQx# line has a separate Route Control
Register.
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or
15. Each PIRQx# line has a separate Route Control
Register.
In the APIC mode, these signals are connected to
the internal I/O APIC, as follows: PIRQ[A]# is
connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]#
to IRQ18, and PIRQ[D]# to IRQ19. This frees the
ISA interrupts.
the internal I/O APIC, as follows: PIRQ[A]# is
connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]#
to IRQ18, and PIRQ[D]# to IRQ19. This frees the
ISA interrupts.
PIRQ#[G:F] /
GPIO[4:3]
These signals require a pull-up
resistor. Recommend a 2.7 k
resistor. Recommend a 2.7 k
Ω
pull-up resistor to V
CC
5 or an
8.2 k
Ω
pull-up resistor to V
CC
3.3.
In non-APIC mode, the PIRQx# signals can be
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or
15. Each PIRQx# line has a separate Route Control
Register.
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or
15. Each PIRQx# line has a separate Route Control
Register.
In APIC mode, these signals are connected to the
internal I/O APIC, as follows: PIRQ[E]# is
connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]#
to IRQ22, and PIRQ[H]# to IRQ23. This frees the
ISA interrupts.
internal I/O APIC, as follows: PIRQ[E]# is
connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]#
to IRQ22, and PIRQ[H]# to IRQ23. This frees the
ISA interrupts.
PIRQ#[H]
PIRQ#[E]
These signals require a pull-up
resistor. A 2.7 k
resistor. A 2.7 k
Ω
pull-up resistor
to V
CC
5 or an 8.2 k
Ω
pull-up
resistor to V
CC
3.3 is
recommended.
In a non-APIC mode, the PIRQx# signals can be
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or
15. Each PIRQx# line has a separate Route Control
Register.
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or
15. Each PIRQx# line has a separate Route Control
Register.
In the APIC mode, these signals are connected to
the internal I/O APIC, as follows: PIRQ[E]# is
connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]#
to IRQ22, and PIRQ[H]# to IRQ23. This frees the
ISA interrupts. If not needed for interrupts, these
signals can be used as GPIO.
the internal I/O APIC, as follows: PIRQ[E]# is
connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]#
to IRQ22, and PIRQ[H]# to IRQ23. This frees the
ISA interrupts. If not needed for interrupts, these
signals can be used as GPIO.
APIC
•
If the APIC is used
150
Ω
pull-up resistors on
APICD[0:1] ! Same as
SC242 checklist: PICD[0:1]
SC242 checklist: PICD[0:1]
Connect APICCLK to
CK133, with a 20
CK133, with a 20
Ω
to 33
Ω
series termination resistor.
•
If the APIC is not used on UP
systems
APICCLK can either be tied
to GND or connected to
CK133, but cannot be left
floating.
to GND or connected to
CK133, but cannot be left
floating.
Pull APICD[0:1] to GND
through 10 k
through 10 k
Ω
pull-down
resistors.
If the APIC is not used on UP systems:
Use pull-downs for each APIC signal. Do not share
a resistor to pull-up signals.
a resistor to pull-up signals.