Intel 820E Manuale Utente

Design Guide 

 

129 

THRM# 

Connect to temperature sensor. 
Pull-up if not used.

 

Input to ICH2 cannot float. THRM# 
polarity bit defaults THRM# to active 
low, so pull-up. 

SLP_S3# 

SLP_S5# 

No pull-up/pull-down resistors needed. 
Signals driven by ICH2. 

Signal driven by ICH2. 

PWROK 

This signal should be connected to power 
monitoring logic, and should go high no 
sooner than 10 ms after both Vcc 3_3 and 
Vcc 1_8 have reached their nominal 
voltages 

Timing requirement 

PWRBTN# 

No extra pull-up resistors 

This signal has an integrated pull-up of 9 
k

Ω

 ± 3 k

Ω

. 

RI# 

RI# does not have an internal pull-up. An 
8.2 k

Ω

 pull-up resistor to the resume well is 

recommended. 

If this signal is enabled as a wake event, 
it is important to keep it powered during 
the power loss event. If this signal goes 
low (active), when power returns the 
RI_STS bit will be set and the system 
will interpret that as a wake event. 

RSMRST# 

This signal should be connected to power 
monitoring logic, and it should go high no 
sooner than 10 ms after both VccSus3_3 
and VccSus1_8 have reached their nominal 
voltages. It can be tied to RESUMEPWROK 
on desktop platforms. 

Timing requirement 

  

A20M#, CPUSLP#, 
IGNNE#, INIT#, INTR, 
NMI, SMI#, STPCLK#

 

Internal circuitry has been added to the 
ICH2. External pull-up resistors are not 
needed.

 

Push/pull buffers now drive the output 
signals. 

FERR# 

Requires a weak external pull-up resistor 
to VCC

CORE

.

 

For specific values, refer to the 
processor documentation for the 
processor that the platform utilizes. 

RCIN#

 

A20GATE

 

Pull-up signals to V

CC

 3.3 through a 10 k

Ω

 

resistor 

Typically driven by an open-drain 
external microcontroller. 

CPUPWRGD

 

Connect to the processor PWRGOOD 
input. Requires a weak external pull-up 
resistor to VCC

CORE

.

 

For specific values, refer to the 
processor documentation for the 
processor that the platform utilizes.