Texas Instruments TMS320DM643X DMP Manuale Utente
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4.8
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
MDIO Registers
The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in
and described in
Figure 20. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
31
16
Reserved
R-0
15
2
1
0
Reserved
USERINTMASKED
R-0
R/WC-0
LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset
Table 18. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
USERINTMASKED
Masked value of MDIO User command complete interrupt. When asserted, a bit indicates that
the previously scheduled PHY read or write command using that particular USERACCESS
register has completed and the corresponding USERINTMASKSET bit is set to 1.
USERINTMASKED[0] and USERINTMASKED[1] correspond to USERACCESS0 and
USERACCESS1, respectively. Writing a 1 will clear the interrupt and writing a 0 has no effect.
the previously scheduled PHY read or write command using that particular USERACCESS
register has completed and the corresponding USERINTMASKSET bit is set to 1.
USERINTMASKED[0] and USERINTMASKED[1] correspond to USERACCESS0 and
USERACCESS1, respectively. Writing a 1 will clear the interrupt and writing a 0 has no effect.
0
No MDIO user command complete event.
1
The previously scheduled PHY read or write command using MDIO user access register n
(USERACCESSn) has completed and the corresponding bit in USERINTMASKSET is set to 1.
(USERACCESSn) has completed and the corresponding bit in USERINTMASKSET is set to 1.
SPRU941A – April 2007
Ethernet Media Access Controller (EMAC)/
61
Management Data Input/Output (MDIO)