Manuali utente per Texas Instruments TMS320DM643X DMP

Sommario

• Table of Contents

  3
• Preface

  10
• 1 Introduction

  11
  • 1.1 Purpose of the Peripheral

    11
  • 1.2 Features

    11
  • 1.3 Functional Block Diagram

    12
  • 1.4 Industry Standard(s) Compliance Statement

    13
• 2 Peripheral Architecture

  13
  • 2.1 Clock Control

    13
  • 2.2 Memory Map

    13
  • 2.3 Signal Descriptions

    13
  • 2.4 Ethernet Protocol Overview

    15
    • 2.4.1 Ethernet Frame Format

      15
    • 2.4.2 Ethernet’s Multiple Access Protocol

      16
  • 2.5 Programming Interface

    16
    • 2.5.1 Packet Buffer Descriptors

      16
    • 2.5.2 Transmit and Receive Descriptor Queues

      18
    • 2.5.3 Transmit and Receive EMAC Interrupts

      19
    • 2.5.4 Transmit Buffer Descriptor Format

      20
      • 2.5.4.1 Next Descriptor Pointer

        21
      • 2.5.4.2 Buffer Pointer

        21
      • 2.5.4.3 Buffer Offset

        21
      • 2.5.4.4 Buffer Length

        21
      • 2.5.4.5 Packet Length

        21
      • 2.5.4.6 Start of Packet (SOP) Flag

        21
      • 2.5.4.7 End of Packet (EOP) Flag

        22
      • 2.5.4.8 Ownership (OWNER) Flag

        22
      • 2.5.4.9 End of Queue (EOQ) Flag

        22
      • 2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag

        22
      • 2.5.4.11 Pass CRC (PASSCRC) Flag

        22
    • 2.5.5 Receive Buffer Descriptor Format

      23
      • 2.5.5.1 Next Descriptor Pointer

        23
      • 2.5.5.2 Buffer Pointer

        23
      • 2.5.5.3 Buffer Offset

        24
      • 2.5.5.4 Buffer Length

        25
      • 2.5.5.5 Packet Length

        25
      • 2.5.5.6 Start of Packet (SOP) Flag

        25
      • 2.5.5.7 End of Packet (EOP) Flag

        25
      • 2.5.5.8 Ownership (OWNER) Flag

        25
      • 2.5.5.9 End of Queue (EOQ) Flag

        25
      • 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag

        26
      • 2.5.5.11 Pass CRC (PASSCRC) Flag

        26
      • 2.5.5.12 Jabber Flag

        26
      • 2.5.5.13 Oversize Flag

        26
      • 2.5.5.14 Fragment Flag

        26
      • 2.5.5.15 Undersized Flag

        26
      • 2.5.5.16 Control Flag

        26
      • 2.5.5.17 Overrun Flag

        26
      • 2.5.5.18  Code Error (CODEERROR) Flag

        26
      • 2.5.5.19  Alignment Error (ALIGNERROR) Flag

        26
      • 2.5.5.20  CRC Error (CRCERROR) Flag

        26
      • 2.5.5.21  No Match (NOMATCH) Flag

        27
  • 2.6 EMAC Control Module

    27
    • 2.6.1 Internal Memory

      27
    • 2.6.2 Bus Arbiter

      27
    • 2.6.3 Interrupt Control

      28
  • 2.7 MDIO Module

    28
    • 2.7.1 MDIO Module Components

      28
      • 2.7.1.1 MDIO Clock Generator

        29
      • 2.7.1.2 Global PHY Detection and Link State Monitoring

        29
      • 2.7.1.3 Active PHY Monitoring

        29
      • 2.7.1.4 PHY Register User Access

        29
    • 2.7.2 MDIO Module Operational Overview

      30
      • 2.7.2.1 Initializing the MDIO Module

        31
      • 2.7.2.2 Writing Data To a PHY Register

        31
      • 2.7.2.3 Reading Data From a PHY Register

        31
      • 2.7.2.4 Example of MDIO Register Access Code

        32
  • 2.8 EMAC Module

    33
    • 2.8.1 EMAC Module Components

      33
      • 2.8.1.1 Receive DMA Engine

        33
      • 2.8.1.2 Receive FIFO

        33
      • 2.8.1.3 MAC Receiver

        33
      • 2.8.1.4 Transmit DMA Engine

        34
      • 2.8.1.5 Transmit FIFO

        34
      • 2.8.1.6 MAC Transmitter

        34
      • 2.8.1.7 Statistics Logic

        34
      • 2.8.1.8 State RAM

        34
      • 2.8.1.9 EMAC Interrupt Controller

        34
      • 2.8.1.10 Control Registers and Logic

        34
      • 2.8.1.11 Clock and Reset Logic

        34
    • 2.8.2 EMAC Module Operational Overview

      34
  • 2.9 Media Independent Interface (MII)

    35
    • 2.9.1 Data Reception

      35
      • 2.9.1.1 Receive Control

        35
      • 2.9.1.2 Receive Inter-Frame Interval

        35
      • 2.9.1.3 Receive Flow Control

        35
    • 2.9.2 Data Transmission

      37
      • 2.9.2.1 Transmit Control

        37
      • 2.9.2.2 CRC Insertion

        37
      • 2.9.2.3 Adaptive Performance Optimization (APO)

        37
      • 2.9.2.4 Interpacket-Gap (IPG) Enforcement

        37
      • 2.9.2.5 Back Off

        37
      • 2.9.2.6 Transmit Flow Control

        38
      • 2.9.2.7 Speed, Duplex, and Pause Frame Support

        38
  • 2.10 Packet Receive Operation

    39
    • 2.10.1 Receive DMA Host Configuration

      39
    • 2.10.2 Receive Channel Enabling

      39
    • 2.10.3 Receive Address Matching

      39
    • 2.10.4 Hardware Receive QOS Support

      40
    • 2.10.5 Host Free Buffer Tracking

      40
    • 2.10.6 Receive Channel Teardown

      40
    • 2.10.7 Receive Frame Classification

      41
    • 2.10.8 Promiscuous Receive Mode

      41
    • 2.10.9 Receive Overrun

      43
  • 2.11 Packet Transmit Operation

    44
    • 2.11.1 Transmit DMA Host Configuration

      44
    • 2.11.2 Transmit Channel Teardown

      44
  • 2.12 Receive and Transmit Latency

    44
  • 2.13 Transfer Node Priority

    45
  • 2.14 Reset Considerations

    45
    • 2.14.1 Software Reset Considerations

      45
    • 2.14.2 Hardware Reset Considerations

      46
  • 2.15 Initialization

    46
    • 2.15.1 Enabling the EMAC/MDIO Peripheral

      46
    • 2.15.2 EMAC Control Module Initialization

      46
    • 2.15.3 MDIO Module Initialization

      47
    • 2.15.4 EMAC Module Initialization

      48
  • 2.16 Interrupt Support

    49
    • 2.16.1 EMAC Module Interrupt Events and Requests

      49
      • 2.16.1.1 Transmit Packet Completion Interrupts

        49
      • 2.16.1.2 Receive Packet Completion Interrupts

        49
      • 2.16.1.3 Statistics Interrupt

        50
      • 2.16.1.4 Host Error Interrupt

        50
    • 2.16.2 MDIO Module Interrupt Events and Requests

      51
      • 2.16.2.1 Link Change Interrupt

        51
      • 2.16.2.2 User Access Completion Interrupt

        51
    • 2.16.3 Proper Interrupt Processing

      51
    • 2.16.4 Interrupt Multiplexing

      51
  • 2.17 Power Management

    52
  • 2.18 Emulation Considerations

    52
• 3 EMAC Control Module Registers

  53
  • 3.1 EMAC Control Module Interrupt Control Register (EWCTL)

    53
  • 3.2 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)

    54
• 4 MDIO Registers

  55
  • 4.1 MDIO Version Register (VERSION)

    55
  • 4.2 MDIO Control Register (CONTROL)

    56
  • 4.3 PHY Acknowledge Status Register (ALIVE)

    57
  • 4.4 PHY Link Status Register (LINK)

    57
  • 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)

    58
  • 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)

    59
  • 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)

    60
  • 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

    61
  • 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)

    62
  • 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

    63
  • 4.11 MDIO User Access Register 0 (USERACCESS0)

    64
  • 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0)

    65
  • 4.13 MDIO User Access Register 1 (USERACCESS1)

    66
  • 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)

    67
• 5 Ethernet Media Access Controller (EMAC) Registers

  68
  • 5.1 Transmit Identification and Version Register (TXIDVER)

    71
  • 5.2 Transmit Control Register (TXCONTROL)

    71
  • 5.3 Transmit Teardown Register (TXTEARDOWN)

    72
  • 5.4 Receive Identification and Version Register (RXIDVER)

    73
  • 5.5 Receive Control Register (RXCONTROL)

    73
  • 5.6 Receive Teardown Register (RXTEARDOWN)

    74
  • 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)

    75
  • 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)

    76
  • 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)

    77
  • 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)

    78
  • 5.11 MAC Input Vector Register (MACINVECTOR)

    79
  • 5.12 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)

    80
  • 5.13 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)

    81
  • 5.14 Receive Interrupt Mask Set Register (RXINTMASKSET)

    82
  • 5.15 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

    83
  • 5.16 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)

    84
  • 5.17 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)

    84
  • 5.18 MAC Interrupt Mask Set Register (MACINTMASKSET)

    85
  • 5.19 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

    85
  • 5.20 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)

    86
  • 5.21 Receive Unicast Enable Set Register (RXUNICASTSET)

    89
  • 5.22 Receive Unicast Clear Register (RXUNICASTCLEAR)

    90
  • 5.23 Receive Maximum Length Register (RXMAXLEN)

    91
  • 5.24 Receive Buffer Offset Register (RXBUFFEROFFSET)

    91
  • 5.25 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)

    92
  • 5.26 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)

    92
  • 5.27 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

    93
  • 5.28 MAC Control Register (MACCONTROL)

    94
  • 5.29 MAC Status Register (MACSTATUS)

    96
  • 5.30 Emulation Control Register (EMCONTROL)

    98
  • 5.31 FIFO Control Register (FIFOCONTROL)

    98
  • 5.32 MAC Configuration Register (MACCONFIG)

    99
  • 5.33 Soft Reset Register (SOFTRESET)

    99
  • 5.34 MAC Source Address Low Bytes Register (MACSRCADDRLO)

    100
  • 5.35 MAC Source Address High Bytes Register (MACSRCADDRHI)

    100
  • 5.36 MAC Hash Address Register 1 (MACHASH1)

    101
  • 5.37 MAC Hash Address Register 2 (MACHASH2)

    101
  • 5.38 Back Off Test Register (BOFFTEST)

    102
  • 5.39 Transmit Pacing Algorithm Test Register (TPACETEST)

    102
  • 5.40 Receive Pause Timer Register (RXPAUSE)

    103
  • 5.41 Transmit Pause Timer Register (TXPAUSE)

    103
  • 5.42 MAC Address Low Bytes Register (MACADDRLO)

    104
  • 5.43 MAC Address High Bytes Register (MACADDRHI)

    104
  • 5.44 MAC Index Register (MACINDEX)

    105
  • 5.45 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)

    106
  • 5.46 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)

    106
  • 5.47 Transmit Channel 0-7 Completion Pointer Register (TXnCP)

    107
  • 5.48 Receive Channel 0-7 Completion Pointer Register (RXnCP)

    107
  • 5.49 Network Statistics Registers

    108
    • 5.49.1 Good Receive Frames Register (RXGOODFRAMES)

      108
    • 5.49.2 Broadcast Receive Frames Register (RXBCASTFRAMES)

      108
    • 5.49.3 Multicast Receive Frames Register (RXMCASTFRAMES)

      108
    • 5.49.4 Pause Receive Frames Register (RXPAUSEFRAMES)

      109
    • 5.49.5 Receive CRC Errors Register (RXCRCERRORS)

      109
    • 5.49.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)

      109
    • 5.49.7 Receive Oversized Frames Register (RXOVERSIZED)

      109
    • 5.49.8 Receive Jabber Frames Register (RXJABBER)

      110
    • 5.49.9 Receive Undersized Frames Register (RXUNDERSIZED)

      110
    • 5.49.10 Receive Frame Fragments Register (RXFRAGMENTS)

      110
    • 5.49.11 Filtered Receive Frames Register (RXFILTERED)

      110
    • 5.49.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)

      111
    • 5.49.13 Receive Octet Frames Register (RXOCTETS)

      111
    • 5.49.14 Good Transmit Frames Register (TXGOODFRAMES)

      111
    • 5.49.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)

      112
    • 5.49.16 Multicast Transmit Frames Register (TXMCASTFRAMES)

      112
    • 5.49.17 Pause Transmit Frames Register (TXPAUSEFRAMES)

      112
    • 5.49.18 Deferred Transmit Frames Register (TXDEFERRED)

      112
    • 5.49.19 Transmit Collision Frames Register (TXCOLLISION)

      112
    • 5.49.20 Transmit Single Collision Frames Register (TXSINGLECOLL)

      113
    • 5.49.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)

      113
    • 5.49.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL)

      113
    • 5.49.23 Transmit Late Collision Frames Register (TXLATECOLL)

      113
    • 5.49.24 Transmit Underrun Error Register (TXUNDERRUN)

      113
    • 5.49.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)

      114
    • 5.49.26 Transmit Octet Frames Register (TXOCTETS)

      114
    • 5.49.27 Transmit and Receive 64 Octet Frames Register (FRAME64)

      114
    • 5.49.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127)

      114
    • 5.49.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255)

      114
    • 5.49.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)

      115
    • 5.49.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)

      115
    • 5.49.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)

      115
    • 5.49.33 Network Octet Frames Register (NETOCTETS)

      115
    • 5.49.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)

      116
    • 5.49.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS)

      116
    • 5.49.36 Receive DMA Overruns Register (RXDMAOVERRUNS)

      116
• Appendix A Glossary

  117
• Appendix B Revision History

  119