Intel 8XC196Lx Manuale Utente

2-7

The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on
the 87C196LA and LB the reset state level of all 41 general-purpose I/O pins has changed from
a weak logic “1” (wk1) to a weak logic “0” (wk0).

The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two
new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper-
ating mode and configure the phase and polarity of the serial clock signals.

The 8XC196Lx’s event processor array (EPA) is functionally identical to that of the 8XC196Jx,
except that it has only two EPA capture/compare channels without pins instead of four. In addi-
tion the LD has no compare-only channels.

The 87C196LB microcontroller has a peripheral not found on the 8XC196Kx microcontrollers or
any other Lx microcontroller, the J1850 peripheral. The J1850 communications controller man-
ages communications between multiple network nodes. This integrated peripheral supports the
10.4 Kb/s VPW (variable pulse-width) medium-speed, class B, in-vehicle network protocol. It
also supports both the standard and in-frame response (IFR) message framing as specified by the
Society of Automotive Engineering (SAE) J1850 (revised May 1994) technical standards.

With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin
compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are 52-lead
versions of 8XC196Kx microcontrollers. For registers that are implemented in both the
8XC196Lx and the 8XC196Jx, configure the 8XC196Lx register as you would for the 8XC196Jx
unless differences are noted in this supplement.