Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Scheda Tecnica

Datasheet

117

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: 652–655h

Default Value:

00000000h

Access:

RO, RW 

Size:

32 bits

Channel 1 CYCTRK ACT registers.

31:28

RO

0h

Reserved 

27:22

RW

000000b

ACT Window Count (C1sd_cr_act_windowcnt): This field indicates the 
window duration (in DRAM clocks) during which the controller counts the # of 
activate commands which are launched to a particular rank. If the number of 
activate commands launched within this window is greater than 4, then a check 
is implemented to block launch of further activates to this rank for the rest of the 
duration of this window. 

21

RW

0b

Max ACT Check Disable (C1sd_cr_maxact_dischk):This field enables the 
check which ensures that there are no more than four activates to a particular 
rank in a given window. 

20:17

RW

0000b

ACT to ACT Delayed (C1sd_cr_act_act[): This field indicates the minimum 
allowed spacing (in DRAM clocks) between two ACT commands to the same 
rank. Corresponds to t

RRD

 in the DDR Specification.

16:13

RW

0000b

PRE to ACT Delayed (C1sd_cr_pre_act): This field indicates the minimum 
allowed spacing (in DRAM clocks) between the PRE and ACT commands to the 
same rank-bank:12:9R/W0000bPRE-ALL to ACT Delayed 
(C1sd_cr_preall_act):This field indicates the minimum allowed spacing (in DRAM 
clocks) between the PRE-ALL and ACT commands to the same rank. This field 
corresponds to t

RP

 in the DDR Specification.

12:9

RW

0h

ALLPRE to ACT Delay (C1sd_cr_preall_act): From the launch of a 
prechargeall command wait for these many # of mclks before launching a 
activate command. This field corresponds to t

PALL_RP

.

8:0

RW

0000000

00b

REF to ACT Delayed (C1sd_cr_rfsh_act): This field indicates the minimum 
allowed spacing (in DRAM clocks) between REF and ACT commands to the same 
rank. This field corresponds to t

RFC

 in the DDR Specification.