Scheda Tecnica (P4X-UPE3210-316-6M1333)SommarioIntel® 3200 and 3210 Chipset1Contents3Figures11Tables11Revision History131 Introduction151.1 Terminology171.2 MCH Overview201.2.1 Host Interface201.2.2 System Memory Interface201.2.3 Direct Media Interface (DMI)211.2.4 PCI Express* Interface221.2.5 MCH Clocking231.2.6 Power Management231.2.7 Thermal Sensor232 Signal Description252.1 Host Interface Signals262.2 System Memory (DDR2) Interface Signals292.2.1 System Memory Channel A Interface Signals292.2.2 System Memory Channel B Interface Signals302.2.3 System Memory Miscellaneous Signals312.3 PCI Express* Interface Signals312.4 Controller Link Interface Signals322.5 Clocks, Reset, and Miscellaneous322.6 Direct Media Interface332.7 Power and Grounds343 System Address Map353.1 Legacy Address Range383.1.1 DOS Range (0h - 9_FFFFh)383.1.2 Expansion Area (C_0000h-D_FFFFh)393.1.3 Extended System BIOS Area (E_0000h-E_FFFFh)393.1.4 System BIOS Area (F_0000h-F_FFFFh)403.1.5 PAM Memory Area Details403.2 Main Memory Address Range (1MB - TOLUD)403.2.1 ISA Hole (15 MB -16 MB)413.2.2 TSEG423.2.3 Pre-allocated Memory423.3 PCI Memory Address Range (TOLUD - 4 GB)433.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh)453.3.2 HSEG (FEDA_0000h-FEDB_FFFFh)453.3.3 FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF)453.3.4 High BIOS Area453.4 Main Memory Address Space (4 GB to TOUUD)463.4.1 Memory Re-claim Background473.4.2 Memory Reclaiming473.5 PCI Express* Configuration Address Space473.6 PCI Express* Address Space483.7 System Management Mode (SMM)493.7.1 SMM Space Definition493.7.2 SMM Space Restrictions503.7.3 SMM Space Combinations503.7.4 SMM Control Combinations513.7.5 SMM Space Decode and Transaction Handling513.7.6 Processor WB Transaction to an Enabled SMM Address Space513.7.7 SMM Access Through TLB513.8 Memory Shadowing523.9 I/O Address Space523.9.1 PCI Express* I/O Address Mapping534 MCH Register Description554.1 Register Terminology564.2 Configuration Process and Registers574.2.1 Platform Configuration Structure574.3 Configuration Mechanisms584.3.1 Standard PCI Configuration Mechanism584.3.2 PCI Express Enhanced Configuration Mechanism594.4 Routing Configuration Accesses604.4.1 Internal Device Configuration Accesses614.4.2 Bridge Related Configuration Accesses624.5 I/O Mapped Registers634.5.1 CONFIG_ADDRESS-Configuration Address Register634.5.2 CONFIG_DATA-Configuration Data Register645 DRAM Controller Registers (D0:F0)655.1 Configuration Register Details675.1.1 VID-Vendor Identification675.1.2 DID-Device Identification675.1.3 PCICMD-PCI Command685.1.4 PCISTS-PCI Status695.1.5 RID-Revision Identification705.1.6 CC-Class Code705.1.7 MLT-Master Latency Timer705.1.8 HDR-Header Type715.1.9 SVID-Subsystem Vendor Identification715.1.10 SID-Subsystem Identification715.1.11 CAPPTR-Capabilities Pointer725.1.12 PXPEPBAR-PCI Express* Egress Port Base Address725.1.13 MCHBAR-MCH Memory Mapped Register Range Base735.1.14 DEVEN-Device Enable745.1.15 PCIEXBAR-PCI Express* Register Range Base Address755.1.16 DMIBAR-Root Complex Register Range Base Address775.1.17 PAM0-Programmable Attribute Map 0785.1.18 PAM1-Programmable Attribute Map 1795.1.19 PAM2-Programmable Attribute Map 2805.1.20 PAM3-Programmable Attribute Map 3815.1.21 PAM4-Programmable Attribute Map 4825.1.22 PAM5-Programmable Attribute Map 5835.1.23 PAM6-Programmable Attribute Map 6845.1.24 LAC-Legacy Access Control845.1.25 REMAPBASE-Remap Base Address Register855.1.26 REMAPLIMIT-Remap Limit Address Register855.1.27 SMRAM-System Management RAM Control865.1.28 ESMRAMC-Extended System Management RAM Control875.1.29 TOM-Top of Memory885.1.30 TOUUD-Top of Upper Usable Dram885.1.31 BSM-Base of Stolen Memory895.1.32 TSEGMB-TSEG Memory Base895.1.33 TOLUD-Top of Low Usable DRAM905.1.34 ERRSTS-Error Status915.1.35 ERRCMD-Error Command935.1.36 SMICMD-SMI Command945.1.37 SKPD-Scratchpad Data945.1.38 CAPID0-Capability Identifier955.2 MCHBAR985.2.1 CHDECMISC-Channel Decode Misc1005.2.2 C0DRB0-Channel 0 DRAM Rank Boundary Address 01015.2.3 C0DRB1-Channel 0 DRAM Rank Boundary Address 11025.2.4 C0DRB2-Channel 0 DRAM Rank Boundary Address 21035.2.5 C0DRB3-Channel 0 DRAM Rank Boundary Address 31035.2.6 C0DRA01-Channel 0 DRAM Rank 0,1 Attribute1045.2.7 C0DRA23-Channel 0 DRAM Rank 2,3 Attribute1055.2.8 C0CYCTRKPCHG-Channel 0 CYCTRK PCHG1055.2.9 C0CYCTRKACT-Channel 0 CYCTRK ACT1065.2.10 C0CYCTRKWR-Channel 0 CYCTRK WR1075.2.11 C0CYCTRKRD-Channel 0 CYCTRK READ1085.2.12 C0CYCTRKREFR-Channel 0 CYCTRK REFR1085.2.13 C0CKECTRL-Channel 0 CKE Control1095.2.14 C0REFRCTRL-Channel 0 DRAM Refresh Control1105.2.15 C0ECCERRLOG-Channel 0 ECC Error Log1125.2.16 C0ODTCTRL-Channel 0 ODT Control1135.2.17 C1DRB0-Channel 1 DRAM Rank Boundary Address 01135.2.18 C1DRB1-Channel 1 DRAM Rank Boundary Address 11145.2.19 C1DRB2-Channel 1 DRAM Rank Boundary Address 21145.2.20 C1DRB3-Channel 1 DRAM Rank Boundary Address 31155.2.21 C1DRA01-Channel 1 DRAM Rank 0,1 Attributes1155.2.22 C1DRA23-Channel 1 DRAM Rank 2,3 Attributes1155.2.23 C1CYCTRKPCHG-Channel 1 CYCTRK PCHG1165.2.24 C1CYCTRKACT-Channel 1 CYCTRK ACT1175.2.25 C1CYCTRKWR-Channel 1 CYCTRK WR1185.2.26 C1CYCTRKRD-Channel 1 CYCTRK READ1185.2.27 C1CKECTRL-Channel 1 CKE Control1195.2.28 C1REFRCTRL-Channel 1 DRAM Refresh Control1205.2.29 C1ECCERRLOG-Channel 1 ECC Error Log1215.2.30 C1ODTCTRL-Channel 1 ODT Control1225.2.31 EPC0DRB0-EP Channel 0 DRAM Rank Boundary Address 01235.2.32 EPC0DRB1-EP Channel 0 DRAM Rank Boundary Address 11235.2.33 EPC0DRB2-EP Channel 0 DRAM Rank Boundary Address 21235.2.34 EPC0DRB3-EP Channel 0 DRAM Rank Boundary Address 31245.2.35 EPC0DRA01-EP Channel 0 DRAM Rank 0,1 Attribute1245.2.36 EPC0DRA23-EP Channel 0 DRAM Rank 2,3 Attribute1255.2.37 EPDCYCTRKWRTPRE-EPD CYCTRK WRT PRE1255.2.38 EPDCYCTRKWRTACT-EPD CYCTRK WRT ACT1265.2.39 EPDCYCTRKWRTWR-EPD CYCTRK WRT WR1265.2.40 EPDCYCTRKWRTREF-EPD CYCTRK WRT REF1275.2.41 EPDCYCTRKWRTRD-EPD CYCTRK WRT READ1275.2.42 EPDCKECONFIGREG-EPD CKE Related Configuration1285.2.43 EPDREFCONFIG-EP DRAM Refresh Configuration1295.2.44 TSC1-Thermal Sensor Control 11315.2.45 TSC2-Thermal Sensor Control 21325.2.46 TSS-Thermal Sensor Status1345.2.47 TSTTP-Thermal Sensor Temperature Trip Point1355.2.48 TCO-Thermal Calibration Offset1365.2.49 THERM1-Thermal Hardware Protection1375.2.50 TIS-Thermal Interrupt Status1375.2.51 TSMICMD-Thermal SMI Command1395.2.52 PMSTS-Power Management Status1405.3 EPBAR1415.3.1 EPESD-EP Element Self Description1415.3.2 EPLE1D-EP Link Entry 1 Description1425.3.3 EPLE1A-EP Link Entry 1 Address1425.3.4 EPLE2D-EP Link Entry 2 Description1435.3.5 EPLE2A-EP Link Entry 2 Address1435.3.6 EPLE3D-EP Link Entry 3 Description1445.3.7 EPLE3A-EP Link Entry 3 Address1456 Host-Primary PCI Express* Bridge Registers (D1:F0)1476.1 VID1-Vendor Identification1496.2 DID1-Device Identification1506.3 PCICMD1-PCI Command1506.4 PCISTS1-PCI Status1526.5 RID1-Revision Identification1536.6 CC1-Class Code1536.7 CL1-Cache Line Size1546.8 HDR1-Header Type1546.9 PBUSN1-Primary Bus Number1546.10 SBUSN1-Secondary Bus Number1556.11 SUBUSN1-Subordinate Bus Number1556.12 IOBASE1-I/O Base Address1566.13 IOLIMIT1-I/O Limit Address1566.14 SSTS1-Secondary Status1576.15 MBASE1-Memory Base Address1586.16 MLIMIT1-Memory Limit Address1596.17 PMBASE1-Prefetchable Memory Base Address1606.18 PMLIMIT1-Prefetchable Memory Limit Address1616.19 PMBASEU1-Prefetchable Memory Base Address Upper1626.20 PMLIMITU1-Prefetchable Memory Limit Address Upper1636.21 CAPPTR1-Capabilities Pointer1636.22 INTRLINE1-Interrupt Line1646.23 INTRPIN1-Interrupt Pin1646.24 BCTRL1-Bridge Control1646.25 PM_CAPID1-Power Management Capabilities1666.26 PM_CS1-Power Management Control/Status1676.27 SS_CAPID-Subsystem ID and Vendor ID Capabilities1686.28 SS-Subsystem ID and Subsystem Vendor ID1686.29 MSI_CAPID-Message Signaled Interrupts Capability ID1696.30 MC-Message Control1696.31 MA-Message Address1706.32 MD-Message Data1706.33 PE_CAPL-PCI Express* Capability List1706.34 PE_CAP-PCI Express* Capabilities1716.35 DCAP-Device Capabilities1716.36 DCTL-Device Control1726.37 DSTS-Device Status1736.38 LCAP-Link Capabilities1746.39 LCTL-Link Control1766.40 LSTS-Link Status1786.41 SLOTCAP-Slot Capabilities1796.42 SLOTCTL-Slot Control1806.43 SLOTSTS-Slot Status1826.44 RCTL-Root Control1836.45 RSTS-Root Status1846.46 PELC-PCI Express Legacy Control1846.47 VCECH-Virtual Channel Enhanced Capability Header1856.48 PVCCAP1-Port VC Capability Register 11856.49 PVCCAP2-Port VC Capability Register 21866.50 PVCCTL-Port VC Control1866.51 VC0RCAP-VC0 Resource Capability1876.52 VC0RCTL-VC0 Resource Control1886.53 VC0RSTS-VC0 Resource Status1896.54 RCLDECH-Root Complex Link Declaration Enhanced1896.55 ESD-Element Self Description1906.56 LE1D-Link Entry 1 Description1906.57 LE1A-Link Entry 1 Address1916.58 PESSTS-PCI Express* Sequence Status1917 Intel Manageability Engine Subsystem PCI (D3:F0,F3)1937.1 HECI Function in ME Subsystem (D3:F0)1937.1.1 ID-Identifiers1947.1.2 CMD-Command1947.1.3 STS-Device Status1957.1.4 RID-Revision ID1957.1.5 CC-Class Code1957.1.6 CLS-Cache Line Size1967.1.7 MLT-Master Latency Timer1967.1.8 HTYPE-Header Type1967.1.9 HECI_MBAR-HECI MMIO Base Address1977.1.10 SS-Sub System Identifiers1977.1.11 CAP-Capabilities Pointer1987.1.12 INTR-Interrupt Information1987.1.13 MGNT-Minimum Grant1987.1.14 MLAT-Maximum Latency1997.1.15 HFS-Host Firmware Status1997.1.16 PID-PCI Power Management Capability ID1997.1.17 PC-PCI Power Management Capabilities2007.1.18 PMCS-PCI Power Management Control And Status2007.1.19 MID-Message Signaled Interrupt Identifiers2017.1.20 MC-Message Signaled Interrupt Message Control2017.1.21 MA-Message Signaled Interrupt Message Address2027.1.22 MUA-Message Signaled Interrupt Upper Address (Optional)2027.1.23 MD-Message Signaled Interrupt Message Data2027.1.24 HIDM-HECI Interrupt Delivery Mode2037.2 KT IO/ Memory Mapped Device Specific Registers [D3:F3]2047.2.1 KTRxBR-KT Receive Buffer2047.2.2 KTTHR-KT Transmit Holding2057.2.3 KTDLLR-KT Divisor Latch LSB2057.2.4 KTIER-KT Interrupt Enable2067.2.5 KTDLMR-KT Divisor Latch MSB2067.2.6 KTIIR-KT Interrupt Identification2077.2.7 KTFCR-KT FIFO Control2087.2.8 KTLCR-KT Line Control2097.2.9 KTMCR-KT Modem Control2107.2.10 KTLSR-KT Line Status2117.2.11 KTMSR-KT Modem Status2127.2.12 KTSCR-KT Scratch2128 Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only)2138.1 VID1-Vendor Identification2158.2 DID1-Device Identification2168.3 PCICMD1-PCI Command2168.4 PCISTS1-PCI Status2188.5 RID1-Revision Identification2198.6 CC1-Class Code2198.7 CL1-Cache Line Size2208.8 HDR1-Header Type2208.9 PBUSN1-Primary Bus Number2208.10 SBUSN1-Secondary Bus Number2218.11 SUBUSN1-Subordinate Bus Number2218.12 IOBASE1-I/O Base Address2228.13 IOLIMIT1-I/O Limit Address2228.14 SSTS1-Secondary Status2238.15 MBASE1-Memory Base Address2248.16 MLIMIT1-Memory Limit Address2258.17 PMBASE1-Prefetchable Memory Base Address Upper2268.18 PMLIMIT1-Prefetchable Memory Limit Address2278.19 PMBASEU1-Prefetchable Memory Base Address Upper2288.20 PMLIMITU1-Prefetchable Memory Limit Address Upper2298.21 CAPPTR1-Capabilities Pointer2308.22 INTRLINE1-Interrupt Line2308.23 INTRPIN1-Interrupt Pin2308.24 BCTRL1-Bridge Control2318.25 PM_CAPID1-Power Management Capabilities2328.26 PM_CS1-Power Management Control/Status2338.27 SS_CAPID-Subsystem ID and Vendor ID Capabilities2348.28 SS-Subsystem ID and Subsystem Vendor ID2348.29 MSI_CAPID-Message Signaled Interrupts Capability ID2358.30 MC-Message Control2358.31 MA-Message Address2368.32 MD-Message Data2368.33 PE_CAPL-PCI Express* Capability List2368.34 PE_CAP-PCI Express* Capabilities2378.35 DCAP-Device Capabilities2378.36 DCTL-Device Control2388.37 DSTS-Device Status2398.38 LCAP-Link Capabilities2408.39 LCTL-Link Control2428.40 LSTS-Link Status2448.41 SLOTCAP-Slot Capabilities2458.42 SLOTCTL-Slot Control2468.43 SLOTSTS-Slot Status2488.44 RCTL-Root Control2498.45 RSTS-Root Status2508.46 PELC-PCI Express Legacy Control2508.47 VCECH-Virtual Channel Enhanced Capability Header2518.48 PVCCAP1-Port VC Capability Register 12518.49 PVCCAP2-Port VC Capability Register 22528.50 PVCCTL-Port VC Control2528.51 VC0RCAP-VC0 Resource Capability2538.52 VC0RCTL-VC0 Resource Control2548.53 VC0RSTS-VC0 Resource Status2558.54 RCLDECH-Root Complex Link Declaration Enhanced2558.55 ESD-Element Self Description2568.56 LE1D-Link Entry 1 Description2578.57 LE1A-Link Entry 1 Address2579 Direct Media Interface (DMI) RCRB2599.1 DMIVCECH-DMI Virtual Channel Enhanced Capability2609.2 DMIPVCCAP1-DMI Port VC Capability Register 12609.3 DMIPVCCTL-DMI Port VC Control2619.4 DMIVC0RCAP-DMI VC0 Resource Capability2619.5 DMIVC0RCTL0-DMI VC0 Resource Control2629.6 DMIVC0RSTS-DMI VC0 Resource Status2639.7 DMIVC1RCAP-DMI VC1 Resource Capability2639.8 DMIVC1RCTL1-DMI VC1 Resource Control2649.9 DMIVC1RSTS-DMI VC1 Resource Status2659.10 DMILCAP-DMI Link Capabilities2659.11 DMILCTL-DMI Link Control2669.12 DMILSTS-DMI Link Status26610 Functional Description26710.1 Host Interface26710.1.1 FSB IOQ Depth26710.1.2 FSB OOQ Depth26710.1.3 FSB GTL+ Termination26710.1.4 FSB Dynamic Bus Inversion26710.1.5 APIC Cluster Mode Support26810.2 System Memory Controller26910.2.1 System Memory Organization Modes26910.2.2 System Memory Technology Supported27010.2.3 Error Checking and Correction27110.3 PCI Express*27410.3.1 PCI Express* Architecture27410.4 Thermal Sensor27510.4.1 PCI Device 0, Function 027510.4.2 MCHBAR Thermal Sensor Registers27510.5 Power Management27610.6 Clocking27611 Electrical Characteristics27911.1 Absolute Minimum and Maximum Ratings27911.2 Current Consumption28111.3 Signal Groups28211.4 Buffer Supply and DC Characteristics28511.4.1 I/O Buffer Supply Voltages28511.4.2 General DC Characteristics28612 Ballout and Package Information28912.1 Ballout Information28912.2 Package Information31313 Testability31513.1 XOR Test Mode Initialization31513.2 XOR Chain Definition31613.3 XOR Chains31713.4 XOR Chains318Dimensioni: 2,15 MBPagine: 326Language: EnglishApri il manuale