Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Scheda Tecnica
Codici prodotto
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
128
Datasheet
5.2.42
EPDCKECONFIGREG—EPD CKE Related Configuration
B/D/F/Type:
0/0/0/MCHBAR
Address Offset:
A28–A2Ch
Default Value:
00E0000000h
Access:
RW
Size:
40 bits
BIOS Optimal Default
0h
CKE related configuration registers For EPD.
Bit
Access
Default
Value
Description
39:35
RW
00000b
EPDunit TXPDLL Count (EPDTXPDLL): Specifies the delay from precharge
power down exit to a command that requires the DRAM DLL to be operational.
The commands are read/write.
power down exit to a command that requires the DRAM DLL to be operational.
The commands are read/write.
34:32
RW
000b
EPDunit TXP Count (EPDCKETXP): Specifies the timing requirement for
Active power down exit or fast exit pre-charge power down exit to any command
or slow exit pre-charge power down to Non-DLL (rd/wr/odt) command.
Active power down exit or fast exit pre-charge power down exit to any command
or slow exit pre-charge power down to Non-DLL (rd/wr/odt) command.
31:29
RW
111b
Mode Select (sd0_cr_sms): Mode Select register: This configuration setting
indicates the mode in which the controller is operating in.
111 = Indicates normal mode of operation, else special mode of operation.
indicates the mode in which the controller is operating in.
111 = Indicates normal mode of operation, else special mode of operation.
28:27
RW
00b
EPDunit EMRS Command Select. (EPDEMRSSEL): EMRS mode to select
BANK address.
01 = EMRS
10 = EMRS2
11 = EMRS3
BANK address.
01 = EMRS
10 = EMRS2
11 = EMRS3
26:24
RW
000b
CKE Pulse Width Requirement in High Phase (sd0_cr_cke_pw_hl_safe):
This field indicates CKE pulse width requirement in high phase.
This field indicates CKE pulse width requirement in high phase.
23:20
RW
0h
One-Hot Active Rank Population (ep_scr_actrank): This field indicates the
active rank in a one hot manner
active rank in a one hot manner
19:17
RW
000b
CKE Pulse Width Requirement in Low Phase (sd0_cr_cke_pw_lh_safe):
This field indicates CKE pulse width requirement in low phase.
This field indicates CKE pulse width requirement in low phase.
16:15
RO
0h
Reserved
14
RW
0b
EPDunit MPR Mode (EPDMPR): MPR Read Mode
1 = MPR mode
0 = Normal mode
In MPR mode, only read cycles must be issued by Firmware. Page Results are
ignored by DCS and just issues the read chip select.
1 = MPR mode
0 = Normal mode
In MPR mode, only read cycles must be issued by Firmware. Page Results are
ignored by DCS and just issues the read chip select.
13
RW
0b
EPDunit Power Down enable for ODT Rank (EPDOAPDEN): Configuration
to enable the ODT ranks to dynamically enter power down.
1 = Enable active power down.
0 = Disable active power down.
to enable the ODT ranks to dynamically enter power down.
1 = Enable active power down.
0 = Disable active power down.
12
RW
0b
EPDunit Power Down enable for Active Rank (EPDAAPDEN): Configuration
to enable the active rank to dynamically enter power down.
1 = Enable active power down.
0 = Disable active power down.
to enable the active rank to dynamically enter power down.
1 = Enable active power down.
0 = Disable active power down.
11:10
RO
0h
Reserved
9:1
RW
0000000
00b
Self Refresh Exit Count (sd0_cr_slfrfsh_exit_cnt): This field indicates the
Self refresh exit count. (Program to 255)
Self refresh exit count. (Program to 255)