Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Scheda Tecnica

132

Datasheet

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: CD9h

Default Value:

00h

Access:

RO, RW/L 

Size:

8 bits

This register controls the operation of the thermal sensor.

All bits in this register are reset to their defaults by MPWROK.

0

RS/WC

0b

In Use (IU): Software semaphore bit. 
After a full MCH RESET, a read to this bit returns a 0. 
After the first read, subsequent reads will return a 1. 
A write of a 1 to this bit will reset the next read value to 0. 
Writing a 0 to this bit has no effect. 
Software can poll this bit until it reads a 0, and will then own the usage of the 
thermal sensor. 
This bit has no other effect on the hardware, and is only used as a semaphore 
among various independent software threads that may need to use the thermal 
sensor. 
Software that reads this register but does not intend to claim exclusive access of 
the thermal sensor must write a one to this bit if it reads a 0, in order to allow 
other software threads to claim it. 
See also THERM3 bit 7 and IUB, which are independent additional semaphore 
bits.

7:4

RO

0h

Reserved