Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Scheda Tecnica

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Datasheet

The role of a MCH in a system is to manage the flow of information between its four 

interfaces: the processor interface, the system memory interface, the PCI Express 

interface, and the I/O Controller through DMI interface. This includes arbitrating 

between the four interfaces when each initiates transactions. It supports one or two 

channels of DDR2 SDRAM. It also supports the PCI Express based external device 

attach. The Intel 3200/3210 Chipset platform supports the ninth generation I/O 

Controller Hub (Intel ICH9) to provide I/O related features. 

The MCH supports a single LGA775 socket processor. The MCH supports a FSB 

frequency of 800/1066/1333 MHz. Host-initiated I/O cycles are decoded to PCI 

Express, DMI, or the MCH configuration space. Host-initiated memory cycles are 

decoded to PCI Express, DMI or system memory. PCI Express device accesses to non-

cacheable system memory are not snooped on the host bus. Memory accesses initiated 

from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped 

on the host bus.

• Supports the Dual-Core Intel

®

 Xeon

®

 Processor 3000 Series and Quad-Core Intel

®

 

Xeon

®

 Processor 3200 Series. 

• Supports Front Side Bus (FSB) at the following Frequency Ranges:

— 800/1066/1333MT/s

• Supports FSB Dynamic Bus Inversion (DBI)
• Supports 36-bit host bus addressing, allowing the processor to access the entire 

64 GB of the host address space.

• Has a 12-deep In-Order Queue to support up to twelve outstanding pipelined 

address requests on the host bus

• Has a 1-deep Defer Queue
• Uses GTL+ bus driver with integrated GTL termination resistors
• Supports a Cache Line Size of 64 bytes

The MCH integrates a system memory DDR2 controller with two, 64-bit wide interfaces. 

The buffers support SSTL_1.8 (Stub Series Terminated Logic for 1.8 V) signal 

interfaces. The memory controller interface is fully configurable through a set of control 

registers.

• Directly supports one or two channels of DDR2 memory with a maximum of two 

DIMMs per channel.

• Supports single and dual channel memory organization modes.
• Supports a data burst length of eight for all memory organization modes.
• Supports memory data transfer rates of 667 and 800 MHz for DDR2.
• I/O Voltage of 1.8 V for DDR2.
• Supports both un-buffered ECC and non-ECC DDR2 DIMMs. The MCH does not 

support memory configurations that mix ECC and non-ECC un-buffered DIMMs.