Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Scheda Tecnica

Datasheet

33

CL_PWROK

I/O

SSTL

CL Power OK: When asserted, CL_PWROK is an indication to 
the MCH that core power (VCC_CL) has been stable for at least 
10 us.

EXP_SLR

I

CMOS

PCI Express* Static Lane Reversal/Form Factor 
Selection: MCH’s PCI Express lane numbers are reversed to 
differentiate BTX and ATX form factors
0 = MCH PCI Express lane numbers are reversed (BTX)
1 = Normal operation (ATX)

BSEL[2:0]

I

CMOS

Bus Speed Select: At the de-assertion of PWROK, the value 
sampled on these pins determines the expected frequency of 
the bus. 

PWROK

I/O

SSTL

Power OK: When asserted, PWROK is an indication to the MCH 
that core power has been stable for at least 10 us.

ICH_SYNCB

O

HVCMOS

ICH Sync: This signal synchronizes the MCH with the ICH.

ALLZTEST

I

GTL+

All Z Test: This signal is used for chipset Bed of Nails testing to 
execute All Z Test. It is used as output for XOR Chain testing.

XORTEST

I

GTL+

XOR Chain Test: This signal is used for chipset Bed of Nails 
testing to execute XOR Chain Test.

TEST[3:0]

I/O

A

In Circuit Test: These pins should be connected to test points 
on the motherboard. They are internally shorted to the package 
ground and can be used to determine if the corner balls on the 
MCH are correctly soldered down to the motherboard. These 
pins should NOT connect to ground on the motherboard. If 
TEST[3:0] are not going to be used, they should be left as no 
connects.

DMI_RXP_[3:0]
DMI_RXN_[3:0]

I

DMI

Direct Media Interface: Receive differential pair (RX). MCH-
ICH serial interface input

DMI_TXP_[3:0]
DMI_TXN_[3:0]

O

DMI

Direct Media Interface: Transmit differential pair (TX). 
MCH-ICH serial interface output