Intel 220 LE80557RE009512 Scheda Tecnica

Datasheet

53

BPM[2:1]#

BPM[3,0]#

Output

Input/

Output

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance 
monitor signals. They are outputs from the processor which indicate 
the status of breakpoints and programmable counters used for 
monitoring processor performance. BPM[3:0]# should connect the 
appropriate pins of all Celeron FSB agents.This includes debug or 
performance monitoring tools.

BPRI#

Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the 
FSB. It must connect the appropriate pins of both FSB agents. 
Observing BPRI# active (as asserted by the priority agent) causes 
the other agent to stop issuing new requests, unless such requests 
are part of an ongoing locked operation. The priority agent keeps 
BPRI# asserted until all of its requests are completed, then releases 
the bus by de-asserting BPRI#.

BR0#

Input/

Output

BR0# is used by the processor to request the bus. The arbitration is 
done between Celeron (Symmetric Agent) and northbridge (High 
Priority Agent). 
This signal does not have on-die termination and must be 
terminated. 

BSEL[2:0]

Output

BSEL[2:0] (Bus Select) are used to select the processor input clock 
frequency. 

 defines the possible combinations of the signals 

and the frequency associated with each combination. The required 
frequency is determined by the processor, chipset and clock 
synthesizer. All agents must operate at the same frequency. The 
Celeron processor 200 sequence operates at a 533-MHz system bus 
frequency (133-MHz BCLK[1:0] frequency). 

COMP[3:0]

Analog

COMP[3:0] must be terminated on the system board using precision 
(1% tolerance) resistors. 

D[63:0]#

Input/

Output

D[63:0]# (Data) are the data signals. These signals provide a 64-bit 
data path between the FSB agents, and must connect the 
appropriate pins on both agents. The data driver asserts DRDY# to 
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four 
times in a common clock period. D[63:0]# are latched off the falling 
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data 
signals correspond to a pair of one DSTBP# and one DSTBN#. The 
following table shows the grouping of data signals to data strobes 
and DINV#.

Furthermore, the DINV# pins determine the polarity of the data 
signals. Each group of 16 data signals corresponds to one DINV# 
signal. When the DINV# signal is active, the corresponding data 
group is inverted and therefore sampled active high. 

D[15:0]#

0

0

D[31:16]#

1

1

D[47:32]#

2

2

D[63:48]#

3

3