SMSC LAN9311 Manuale Utente

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

174

SMSC LAN9311/LAN9311i

 

Register bits designated as NASR are not reset when either the SRST bit in the 

 register or the DIGITAL_RST bit in the 

 is set.

4

IRQ Polarity (IRQ_POL)
When cleared, this bit enables the IRQ line to function as an active low 
output. When set, the IRQ output is active high. When the IRQ is configured 
as an open-drain output (via the IRQ_TYPE bit), this bit is ignored, and the 
interrupt is always active low.

R/W

NASR

0b

3:1

RO

-

0

IRQ Buffer Type (IRQ_TYPE)
When this bit is cleared, the IRQ pin functions as an open-drain output for 
use in a wired-or interrupt configuration. When set, the IRQ is a push-pull 
driver. 

When configured as an open-drain output, the IRQ_POL bit is 
ignored and the interrupt output is always active low.

R/W

NASR

0b