National Instruments 653X Manuale Utente
Chapter 2
Using Your 653X
2-8
ni.com
To set the direction of the PCLK signal:
•
NI-DAQ C interface—Set the
ND_CLOCK_REVERSE_MODE
to
ND_ON
in
Set_DAQ_Device_Info.
•
LabVIEW—Set the Clock Reverse Mode attribute to ON in the
DIO Parameter VI.
DIO Parameter VI.
Note
For more information on LabVIEW VIs and NI-DAQ functions, consult the
LabVIEW Help and the NI-DAQ Function Reference Help.
Selecting ACK/REQ Signal Polarity
For all handshaking protocols except 8255 emulation, you can set the
polarity of the ACK and REQ signals to Active High or Active Low
through software. By default, these signals are active high in NI-DAQ
functions and active low in LabVIEW VIs. Refer to Table C-1,
polarity of the ACK and REQ signals to Active High or Active Low
through software. By default, these signals are active high in NI-DAQ
functions and active low in LabVIEW VIs. Refer to Table C-1,
, for an overview of all control/timing
trigger lines.
Choosing Whether or Not to Use a Programmable Delay
For all the protocols, you have the option to set a programmable delay.
This is useful when the handshaking signals of the 653X device occur faster
than the peripheral device can handle.
This is useful when the handshaking signals of the 653X device occur faster
than the peripheral device can handle.
For all protocols except burst, the delay increases the time the 653X device
takes to respond to the REQ signal. For the burst protocol, the
programmable delay selects the frequency of the clock signal when you are
using an internally generated clock source. You can change the PCLK
frequency by modifying the ACK Modify Amount parameter of the Digital
Mode Config VI or the ACK Delay Time attribute of the
takes to respond to the REQ signal. For the burst protocol, the
programmable delay selects the frequency of the clock signal when you are
using an internally generated clock source. You can change the PCLK
frequency by modifying the ACK Modify Amount parameter of the Digital
Mode Config VI or the ACK Delay Time attribute of the
DIG_Grp_Mode
function in NI-DAQ C interface. Use the following table to find the
resulting period in nanoseconds. The PCLK frequency is then selected by
the driver based on this choice.
resulting period in nanoseconds. The PCLK frequency is then selected by
the driver based on this choice.
PCLK Period in ns
PCLK Frequency in MHz
50
20
100
10
200
5
300
3.33
400
2.5