Getac Technology Corporation V110GD Manuale Utente

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© 2011 Microchip Technology Inc.
Preliminary
DS61168C-page 167
PIC32MX1XX/2XX
bit 16
ENHBUF: 
Enhanced Buffer Enable bit
(2)
1
 = Enhanced Buffer mode is enabled
0
 = Enhanced Buffer mode is disabled
bit 15
ON: 
SPI Peripheral On bit
(1)
1
 = SPI Peripheral is enabled
0
 = SPI Peripheral is disabled
bit 14
Unimplemented: 
Read as ‘0’
bit 13
SIDL: 
Stop in Idle Mode bit
1
 = Discontinue operation when CPU enters in Idle mode
0
 = Continue operation in Idle mode
bit 12
DISSDO: 
Disable SDOx pin bit
1
 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0
 = SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32
 MODE16
 Communication
1
1
24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
1
0
32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
0
1
16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
0
0
16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN = 0:
MODE32
 MODE16
 Communication
1
x
32-bit
0
1
16-bit
0
0
8-bit
bit 9
SMP: 
SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1
 = Input data sampled at end of data output time
0
 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8
CKE: 
SPI Clock Edge Select bit
(3)
1
 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0
 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
bit 7
SSEN:
 Slave Select Enable (Slave mode) bit
1
 = SSx pin used for Slave mode
0
 = SSx pin not used for Slave mode, pin controlled by port function.
bit 6
CKP:
 Clock Polarity Select bit
1
 = Idle state for clock is a high level; active state is a low level
0
 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN:
 Master Mode Enable bit
1
 = Master mode
0
  = Slave  mode
bit 4
DISSDI: 
Disable SDI bit 
1
 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0
 = SDI pin is controlled by the SPI module
REGISTER 16-1:
SPIxCON: SPI CONTROL REGISTER  (CONTINUED)
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in 
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2:
This bit can only be written when the ON bit = 0.
3:
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI 
mode (FRMEN = 1).