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Processor Configuration Registers
104
Datasheet, Volume 2
2.6.25
PM_CAPID—Power Management Capabilities Register
2
RW
0b
Uncore
ISA Enable (ISAEN)
Needed to exclude legacy resource decode to route ISA resources 
to legacy decode path. Modifies the response by the root port to 
an I/O access issued by the processor that target ISA I/O 
addresses. This applies only to I/O addresses that are enabled by 
the IOBASE and IOLIMIT registers. 
0 = All addresses defined by the IOBASE and IOLIMIT for 
processor I/O transactions will be mapped to PCI Express-G.
1 = The root port will not forward to PCI Express-G any I/O 
transactions addressing the last 768 bytes in each 1 KB 
block, even if the addresses are within the range defined by 
the IOBASE and IOLIMIT registers.
1
RW
0b
Uncore
SERR Enable (SERREN)
0 = No forwarding of error messages from secondary side to 
primary side that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result 
in SERR message when individually enabled by the Root 
Control register.
0
RW
0b
Uncore
Parity Error Response Enable (PEREN) 
This bit controls whether or not the Master Data Parity Error bit in 
the Secondary Status register is set when the root port receives 
across the link (upstream) a Read Data Completion Poisoned TLP.
0 = Master Data Parity Error bit in Secondary Status register can 
NOT be set. 
1 = Master Data Parity Error bit in Secondary Status register 
CAN be set.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
80–83h
Reset Value:
C8039001h
Access:
RO, RO-V
Size:
32 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
31:27
RO
19h
Uncore
PME Support (PMES) 
This field indicates the power states in which this device may 
indicate PME wake using PCI Express messaging. D0, D3hot, and 
D3cold. This device is not required to do anything to support 
D3hot and D3cold; it simply must report that those states are 
supported. Refer to the PCI Power Management 1.1 specification 
for encoding explanation and other power management details.
26
RO
0b
Uncore
D2 Power State Support (D2PSS) 
Hardwired to 0 to indicate that the D2 power management state 
is NOT supported.
25
RO
0b
Uncore
D1 Power State Support (D1PSS) 
Hardwired to 0 to indicate that the D1 power management state 
is NOT supported.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
3E–3Fh
Reset Value:
0000h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
0h
Bit
Access
Reset 
Value
RST/
PWR
Description