HP A2Y15AV Manuale Utente

110

Datasheet, Volume 2

This register enumerates the PCI Express* capability structure.

31:2

RW

00000000h

Uncore

Message Address (MA) 
Used by system software to assign an MSI address to the 

device. The device handles an MSI by writing the padded 

contents of the MD register to this address.

1:0

RO

00b

Uncore

Force DWord Align (FDWA) 
Hardwired to 0 so that addresses assigned by system software 

are always aligned on a DWord address boundary.

15:0

RW

0000h

Uncore

Message Data (MD) 
Base message data pattern assigned by system software and 

used to handle an MSI from the device. 
When the device must generate an interrupt request, it writes a 

32-bit value to the memory address specified in the MA register. 

The upper 16 bits are always set to 0. The lower 16 bits are 

supplied by this register.

15:8

RO

00h

Uncore

Pointer to Next Capability (PNC) 
This value terminates the capabilities list. The Virtual Channel 

capability and any other PCI Express specific capabilities that are 

reported using this mechanism are in a separate capabilities list 

located entirely within PCI Express Extended Configuration 

Space.

7:0

RO

10h

Uncore

Capability ID (CID) 
This field identifies this linked list item (capability structure) as 

being for PCI Express registers.