HP A2Y15AV Manuale Utente
Datasheet, Volume 2
187
Processor Configuration Registers
2.10.32 MD—Message Data Register
2.10.33 PEG_CAPL—PCI Express-G Capability List Register
This register enumerates the PCI Express* capability structure.
B/D/F/Type:
0/6/0/PCI
Address Offset:
98–99h
Reset Value:
0000h
Access:
RW
Size:
16 bits
Bit
Access
Reset
Value
RST/
PWR
Description
15:0
RW
0000h
Uncore
Message Data (MD)
Base message data pattern assigned by system software and
Base message data pattern assigned by system software and
used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a
When the device must generate an interrupt request, it writes a
32-bit value to the memory address specified in the MA register.
The upper 16 bits are always set to 0. The lower 16 bits are
supplied by this register.
B/D/F/Type:
0/6/0/PCI
Address Offset:
A0–A1h
Reset Value:
0010h
Access:
RO
Size:
16 bits
Bit
Access
Reset
Value
RST/
PWR
Description
15:8
RO
00h
Uncore
Pointer to Next Capability (PNC)
This value terminates the capabilities list. The Virtual Channel
This value terminates the capabilities list. The Virtual Channel
capability and any other PCI Express specific capabilities that are
reported using this mechanism are in a separate capabilities list
located entirely within PCI Express Extended Configuration
Space.
7:0
RO
10h
Uncore
Capability ID (CID)
This field identifies this linked list item (capability structure) as
This field identifies this linked list item (capability structure) as
being for PCI Express registers.