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HP A2Y15AV Manuale Utente

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Processor Configuration Registers
220
Datasheet, Volume 2
2.12.4
DMIPVCCTL—DMI Port VC Control Register
2.12.5
DMIVC0RCAP—DMI VC0 Resource Capability Register
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
C–Dh
Reset Value:
0000h
Access:
RW, RO
Size:
16 bits
BIOS Optimal Default
000h
Bit
Access
Reset 
Value
RST/
PWR
Description
15:4
RO
0h
Reserved (RSVD) 
3:1
RW
000b
Uncore
VC Arbitration Select (VCAS) 
This field will be programmed by software to the only possible 
value as indicated in the VC Arbitration Capability field.
The value 000b when written to this field will indicate the VC 
arbitration scheme is hardware fixed (in the root complex). This 
field cannot be modified when more than one VC in the LPVC 
group is enabled.
000 = Hardware fixed arbitration scheme, such as Round Robin
Others = Reserved
See the PCI express specification for more details.
0
RO
0b
Uncore
Reserved for Load VC Arbitration Table (LVCAT) 
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
10–13h
Reset Value:
00000001h
Access:
RO
Size:
32 bits
BIOS Optimal Default
00h
Bit
Access
Reset 
Value
RST/
PWR
Description
31:24
RO
00h
Uncore
Reserved for Port Arbitration Table Offset (PATO) 
23
RO
0h
Reserved (RSVD) 
22:16
RO
00h
Uncore
Reserved for Maximum Time Slots (MTS) 
15
RO
0b
Uncore
Reject Snoop Transactions (REJSNPT) 
0 = Transactions with or without the No Snoop bit set within the 
TLP header are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is 
applicable but is not set within the TLP Header will be 
rejected as an Unsupported Request.
14:8
RO
0h
Reserved (RSVD) 
7:0
RO
01h
Uncore
Port Arbitration Capability (PAC) 
Having only bit 0 set indicates that the only supported arbitration 
scheme for this VC is non-configurable hardware-fixed.