HP A2Y15AV Manuale Utente

Datasheet, Volume 2

233

Processor Configuration Registers 

This register provides the second part of a Link Entry that declares an internal link to 
another Root Complex Element.

This register indicates DMI specific capabilities.

31:12

RW-O

00000h

Uncore

Link Address (LA) 
Memory mapped base address of the RCRB that is the target 

element (Egress Port) for this link entry.

11:0

RO

0h

31:18

RO

0h

17:15

RW-O

011b

Uncore

L1 Exit Latency (L1SELAT) 
This field indicates the length of time this Port requires to 

complete the transition from L1 to L0. The value 011b indicates 

the range of 4 us to less than 8 us.
000 = Less than 1µs
001 = 1 µs to less than 2 µs
010 = 2 µs to less than 4 µs
011 = 4 µs to less than 8 µs
100 = 8 µs to less than 16 µs
101 = 16 µs to less than 32 µs
110 = 32 µs-64 µs
111 = More than 64 µs
Both bytes of this register that contain a portion of this field must 

be written simultaneously in order to prevent an intermediate 

(and undesired) value from ever existing.

14:12

RW-O

010b

Uncore

L0s Exit Latency (L0SELAT) 
This field indicates the length of time this Port requires to 

complete the transition from L0s to L0.
000 = Less than 64 ns
001 = 64 ns to less than 128 ns
010 = 128 ns to less than 256 ns
011 = 256 ns to less than 512 ns
100 = 512 ns to less than 1 µs
101 = 1 µs to less than 2 µs
110 = 2 µs-4 µs
111 = More than 4 µs