HP A2Y15AV Manuale Utente

236

Datasheet, Volume 2

15:12

RWS

0000b

Powergood

Compliance De-emphasis (ComplianceDeemphasis) 
For 8 GT/s Data Rate: This field sets the Transmitter Preset 

level in Polling.Compliance state if the entry occurred due to 

the Enter Compliance bit being 1b. The encodings are defined 

in PCIe Specification, Section 4.2.3.2.
For 5 GT/s Data Rate: This bit filed sets the de-emphasis level 

in Polling.Compliance state if the entry occurred due to the 

Enter Compliance bit being 1b.
0001b = -3.5 dB
0000b = -6 dB
When the Link is operating at 2.5 GT/s, the setting of this bit 

has no effect. Components that support only 2.5 GT/s speed 

are permitted to hardwire this bit to 0b.
For a Multi-Function device associated with an Upstream Port, 

the bit in Function 0 is of type RWS, and only Function 0 

controls the component's Link behavior. In all other Functions 

of that device, this bit is of type RsvdP.
The Reset Value of this bit is 0b.
This bit is intended for debug, compliance testing purposes.
System firmware and software is allowed to modify this bit only 

during debug or compliance testing.

11

RWS

0b

Powergood

Compliance SOS (compsos)
When set to 1b, the LTSSM is required to send SKP Ordered 

Sets periodically in between the (modified) compliance 

patterns. For a Multi-Function device associated with an 

Upstream Port, the bit in Function 0 is of type RWS, and only 

Function 0 controls the component's Link behavior. In all other 

Functions of that device, this bit is of type RsvdP. The Reset 

Value of this bit is 0b. Components that support only the 

2.5 GT/s speed are permitted to hardwire this field to 0b.

10

RWS

0b

Powergood

Enter Modified Compliance (entermodcompliance)
When this bit is set to 1b, the device transmits modified 

compliance pattern if the LTSSM enters Polling.Compliance 

state. 
Components that support only the 2.5 GT/s speed are 

permitted to hardwire this bit to 0b. 
Reset Value of this field is 0b.