HP A2Y15AV Manuale Utente

Datasheet, Volume 2

247

Processor Configuration Registers 

This register identifies the I/O latency per rank, and I/O compensation (global).

15:12

RW-L

4h

Uncore

tWTR in DCLK cycles (tWTR) 
Delay from internal WR transaction to internal RD transaction. 

The minimum delay is 4 DCLK cycles, whereas the maximum 

delay is 8 DCLK cycles. 

11:8

RW-L

3h

Uncore

tCKE in DCLK cycles (tCKE) 
CKE minimum pulse width in DCLK cycles. The minimum value is 

3 DCLK cycles, whereas the maximum value is the actual value of 

tXP. 

7:4

RW-L

4h

Uncore

tRTP in DCLK cycles (tRTP) 
Minimum delay from CAS-RD to PRE. The minimum delay is 4 

DCLK cycles, whereas the maximum delay is 8 DCLK cycles. 

3:0

RW-L

4h

Uncore

tRRD in DCLK cycles (tRRD) 
tRRD is the minimum delay between two ACT commands 

targeted to different banks in the same rank. The minimum delay 

is 4 DCLK cycles, whereas the maximum delay is 7 cycles.

31:22

RO

0h

21:16

RW-L

0Eh

Uncore

15:12

RW-L

0h

Uncore

11:8

RW-L

0h

Uncore

7:4

RW-L

0h

Uncore

3:0

RW-L

0h

Uncore