HP A2Y15AV Manuale Utente

Datasheet, Volume 2

287

Processor Configuration Registers 

This register specifies the invalidation event interrupt control bits.

This register is treated as RsvdZ by implementations reporting Queued Invalidation 
(QI) as not supported in the Extended Capability register.

31

RW-L

1b

Uncore

Interrupt Mask (IM) 
0 = No masking of interrupt. When an invalidation event 

condition is detected, hardware issues an interrupt message 

(using the Invalidation Event Data & Invalidation Event 

Address register values).

1 = This is the value on reset. Software may mask interrupt 

message generation by setting this field. Hardware is 

prohibited from sending the interrupt message when this 

field is set. 

30

RO-V

0b

Uncore

Interrupt Pending (IP) 
Hardware sets the IP field whenever it detects an interrupt 

condition. Interrupt condition is defined as:

• An Invalidation Wait Descriptor with Interrupt Flag (IF) field 

set completed, setting the IWC field in the Invalidation 

Completion Status register.

• If the IWC field in the Invalidation Completion Status register 

was already set at the time of setting this field, it is not 

treated as a new interrupt condition.

The IP field is kept set by hardware while the interrupt message 

is held pending. The interrupt message could be held pending 

due to interrupt mask (IM field) being set, or due to other 

transient hardware conditions. The IP field is cleared by hardware 

as soon as the interrupt message pending condition is serviced. 

This could be due to either:

• Hardware issuing the interrupt message due to either change 

in the transient hardware condition that caused interrupt 

message to be held pending or due to software clearing the 

IM field.

• Software servicing the IWC field in the Invalidation 

Completion Status register. 

29:0

RO

0h