HP A2Y15AV Manuale Utente
Processor Configuration Registers
336
Datasheet, Volume 2
2.21.22 ICS_REG—Invalidation Completion Status Register
This register reports completion status of invalidation wait descriptor with Interrupt
Flag (IF) set.
Flag (IF) set.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
(QI) as not supported in the Extended Capability register.
2.21.23 IECTL_REG—Invalidation Event Control Register
This register specifies the invalidation event interrupt control bits.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
(QI) as not supported in the Extended Capability register.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
9C–9Fh
Reset Value:
00000000h
Access:
RW1CS
Size:
32 bits
BIOS Optimal Default
00000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:1
RO
0h
Reserved (RSVD)
0
RW1CS
0b
Powergood
Invalidation Wait Descriptor Complete (IWC)
This bit indicates completion of Invalidation Wait Descriptor
This bit indicates completion of Invalidation Wait Descriptor
with Interrupt Flag (IF) field set. Hardware implementations
not supporting queued invalidations implement this field as
RsvdZ.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
A0–A3h
Reset Value:
80000000h
Access:
RW-L, RO-V
Size:
32 bits
BIOS Optimal Default
00000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31
RW-L
1b
Uncore
Interrupt Mask (IM)
0 = No masking of interrupt. When an invalidation event
0 = No masking of interrupt. When an invalidation event
condition is detected, hardware issues an interrupt message
(using the Invalidation Event Data and Invalidation Event
Address register values).
1 = This is the value on reset. Software may mask interrupt
message generation by setting this field. Hardware is
prohibited from sending the interrupt message when this
field is set.