HP A2Y15AV Manuale Utente

50

Datasheet, Volume 2

This status register reports the occurrence of error events on Device 0's PCI interface. 
Since Device 0 does not physically reside on PCI_A many of the bits are not 
implemented.

7

RO

0b

Uncore

Address/Data Stepping Enable (ADSTEP) 
Address/data stepping is not implemented in the processor, and 

this bit is hardwired to 0. Writes to this bit position have no 

effect.

6

RW

0b

Uncore

Parity Error Enable (PERRE) 
This bit controls whether or not the Master Data Parity Error bit in 

the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT 

be set.

1 = Master Data Parity Error bit in PCI Status register CAN be 

set.

5

RO

0b

Uncore

VGA Palette Snoop Enable (VGASNOOP) 
The processor does not implement this bit and it is hardwired to a 

0. Writes to this bit position have no effect.

4

RO

0b

Uncore

Memory Write and Invalidate Enable (MWIE) 
The processor will never issue memory write and invalidate 

commands. This bit is therefore hardwired to 0. Writes to this bit 

position will have no effect.

3

RO

0h

Reserved (RSVD) 

2

RO

1b

Uncore

Bus Master Enable (BME) 
The processor is always enabled as a master on the backbone. 

This bit is hardwired to a 1. Writes to this bit position have no 

effect.

1

RO

1b

Uncore

Memory Access Enable (MAE) 
The processor always allows access to main memory, except 

when such access would violate security principles. Such 

exceptions are outside the scope of PCI control. This bit is not 

implemented and is hardwired to 1. Writes to this bit position 

have no effect.

0

RO

0b

Uncore

I/O Access Enable (IOAE) 
This bit is not implemented in the processor and is hardwired to a 

0. Writes to this bit position have no effect.

15

RW1C

0b

Uncore

Detected Parity Error (DPE) 
This bit is set when this Device receives a Poisoned TLP.