HP A2Y15AV Manuale Utente

Datasheet, Volume 2

81

Processor Configuration Registers 

This register holds 32 writable bits with no functionality behind them. It is for the 
convenience of BIOS and graphics drivers.

31:20

RW-L

001h

Uncore

Top of Low Usable DRAM (TOLUD) 
This register contains bits 31:20 of an address one byte above 

the maximum DRAM memory below 4 GB that is usable by the 

operating system. Address bits 31:20 programmed to 01h 

implies a minimum memory size of 1 MB. Configuration software 

must set this value to the smaller of the following 2 choices: 

maximum amount memory in the system minus Intel ME stolen 

memory plus one byte or the minimum address allocated for PCI 

memory. Address bits 19:0 are assumed to be 0_0000h for the 

purposes of address comparison. The Host interface positively 

decodes an address towards DRAM if the incoming address is less 

than the value programmed in this register.
The Top of Low Usable DRAM is the lowest address above both 

Graphics Stolen memory and TSEG. BIOS determines the base of 

Graphics Stolen Memory by subtracting the Graphics Stolen 

Memory Size from TOLUD and further decrements by TSEG size 

to determine base of TSEG. All the Bits in this register are locked 

in Intel TXT mode.
This register must be 1 MB aligned when reclaim is enabled.

19:1

RO

0h

0

RW-KL

0b

Uncore

Lock (LOCK): 
This bit will lock all writeable settings in this register, including 

itself.

31:0

RW

00000000h

Uncore

Scratchpad Data (SKPD) 
1 DWord of data storage.