HP A2Y15AV Manuale Utente
Processor Configuration Registers
88
Datasheet, Volume 2
2.6.2
DID—Device Identification Register
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
PCI device.
2.6.3
PCICMD—PCI Command Register
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
2–3h
Reset Value:
0151h
Access:
RO-FW
Size:
16 bits
Bit
Access
Reset
Value
RST/
PWR
Description
15:0
RO-FW
0151h
Uncore
Device Identification Number MSB (DID_MSB)
Identifier assigned to the processor root port (virtual PCI-to-PCI
Identifier assigned to the processor root port (virtual PCI-to-PCI
bridge, PCI Express Graphics port).
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
4–5h
Reset Value:
0000h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
00h
Bit
Access
Reset
Value
RST/
PWR
Description
15:11
RO
0h
Reserved (RSVD)
10
RW
0b
Uncore
INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt
0 = This device is permitted to generate INTA interrupt
messages.
1 = This device is prevented from generating interrupt
messages. Any INTA emulation interrupts already asserted
must be de-asserted when this bit is set.
This bit only affects interrupts generated by the device (PCI INTA
from a PME or Hot-plug event) controlled by this command
register. It does not affect upstream MSIs, upstream PCI INTA-
INTD assert and deassert messages.
Note: PCI Express* Hot-Plug is not supported on the processor.
Note: PCI Express* Hot-Plug is not supported on the processor.
9
RO
0b
Uncore
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.
Not Applicable or Implemented. Hardwired to 0.