HP A2Y15AV Manuale Utente

Datasheet, Volume 2

93

Processor Configuration Registers 

This register identifies the header layout of the configuration space. No physical 
register exists at this location.

This register identifies that this "virtual" Host-PCI Express* bridge is connected to PCI 
bus 0.

This register identifies the bus number assigned to the second bus side of the "virtual" 
bridge; that is, to PCI Express-G. This number is programmed by the PCI configuration 
software to allow mapping of configuration cycles to PCI Express-G.

7:0

RO

81h

Uncore

Header Type Register (HDR) 
Device 1 returns 81h to indicate that this is a multi function 

device with bridge header layout. 
Device 6 returns 01h to indicate that this is a single function 

device with bridge header layout. 

7:0

RO

00h

Uncore

Primary Bus Number (BUSN) 
Configuration software typically programs this field with the 

number of the bus on the primary side of the bridge. Since the 

processor root port is an internal device and its primary bus is 

always 0, these bits are read only and are hardwired to 0. 

7:0

RW

00h

Uncore

Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus 

number assigned to PCI Express-G.