Fujifilm Xeon 5060 S26361-F3312-L320 Scheda Tecnica
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S26361-F3312-L320
Electrical Specifications
24
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
2.7
Front Side Bus Signal Groups
The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DATA and GTLREF_ADD as reference
levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the
AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+
asynchronous outputs can become active anytime and include an active PMOS pull-up
transistor to assist during the first clock of a low-to-high voltage transition.
have differential input buffers, which use GTLREF_DATA and GTLREF_ADD as reference
levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the
AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+
asynchronous outputs can become active anytime and include an active PMOS pull-up
transistor to assist during the first clock of a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and
the second set is for the source synchronous signals which are relative to their
respective strobe lines (data and address) as well as rising edge of BCLK0.
Asynchronous signals are still present (A20M#, IGNNE#, and so forth) and can become
active at any time during the clock cycle.
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and
the second set is for the source synchronous signals which are relative to their
respective strobe lines (data and address) as well as rising edge of BCLK0.
Asynchronous signals are still present (A20M#, IGNNE#, and so forth) and can become
active at any time during the clock cycle.
clock, source synchronous and asynchronous.
Table 2-7.
FSB Signal Groups
Signal Group
Type
Signals
1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#;
AGTL+ Common Clock Output
Synchronous to BCLK[1:0]
BPM4#, BPM[2:1]#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#
2
, BNR#
2
, BPM5#,
BPM3#, BPM0#, BR[1:0]#, DBSY#, DP[3:0]#,
DRDY#, HIT#
2
, HITM#
2
, LOCK#, MCERR#
2
AGTL+ Source Synchronous I/
O
Synchronous to assoc.
strobe
AGTL+ Strobes I/O
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Open Drain Output
Asynchronous
FERR#/PBE#, IERR#, PROCHOT#,
THERMTRIP#
CMOS Asynchronous Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, PWRGOOD, SMI#, STPCLK#,
CMOS Asynchronous Output
Asynchronous
BSEL[2:0], VID[6:1]
FSB Clock
Clock
BCLK[1:0]
TAP Input
Synchronous to TCK
TCK, TDI, TMS, TRST#
TAP Output
Synchronous to TCK
TDO
Power/Other
Power/Other
GTLREF_ADD_MID, GTLREF_ADD_END,
GTLREF_DATA_MID, GTLREF_DATA_END,
LL_ID[1:0], MS_ID[1:0], PECI, RESERVED,
SKTOCC#, TESTHI[11:0], TESTIN1, TESTIN2,
VCC, VCC_DIE_SENSE, VCC_DIE_SENSE2,
VCCPLL, VID_SELECT, VSS_DIE_SENSE,
VSS_DIE_SENSE2, VSS, VTT, VTT_OUT,
VTT_SEL
Signals
Associated Strobe
REQ[4:0]#,A[16:3]
#
ADSTB0#
A[35:17]#
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#