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S26361-F3312-L320
Electrical Specifications
26
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TMS, TDO, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
TCK, TMS, TDO, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
2.10
Platform Environmental Control Interface (PECI)
DC Specifications
The release of the Dual-Core Intel
®
Xeon
®
Processor 5100 Series marks the transition
from thermal diodes to digital thermal sensors for fan speed control. Digital Thermal
Sensors (DTS) are on-die, analog-to-digital temperature converters calibrated at the
factory for reasonable accuracy to provide a digital representation of relative processor
temperature. Data from the DTS are processed and stored in a processor register,
which is queried through the Platform Environment Control Interface (PECI). PECI is a
proprietary one-wire bus interface that provides a communication channel between
Intel processor and chipset components to external thermal monitoring devices. More
detailed information may be found in
Sensors (DTS) are on-die, analog-to-digital temperature converters calibrated at the
factory for reasonable accuracy to provide a digital representation of relative processor
temperature. Data from the DTS are processed and stored in a processor register,
which is queried through the Platform Environment Control Interface (PECI). PECI is a
proprietary one-wire bus interface that provides a communication channel between
Intel processor and chipset components to external thermal monitoring devices. More
detailed information may be found in
2.10.1
DC Characteristics
A PECI device interface operates at a nominal voltage set by V
TT
. The set of DC
is used with devices normally operating
from a V
TT
interface supply. V
TT
nominal levels will vary between processor families. All
PECI devices will operate at the V
TT
level determined by the processor installed in the
system. For specific nominal V
TT
levels, refer to the appropriate processor EMTS.
Note:
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
Table 2-11. PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
1
V
in
Input Voltage Range
-0.150
V
TT
+ 0.150
V
V
hysteresis
Hysteresis
0.1 * V
TT
N/A
V
V
n
Negative-edge threshold
voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold
voltage
0.550 * V
TT
0.725 * V
TT
V
I
source
High level output source
(V
OH
= 0.75 * V
TT
)
-6.0
N/A
mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5
1.0
mA
I
leak+
High impedance state
leakage to V
TT
(V
leak
= V
OL
)
N/A
50
µA
2
I
leak-
High impedance leakage
to GND
(V
leak
= V
OH
)
N/A
10
µA
2
C
bus
Bus capacitance
N/A
10
pF
V
noise
Signal noise immunity
above 300 MHz
0.1 * V
TT
N/A
V
p-p