Fujifilm Xeon S26361-F3099-L828 Scheda Tecnica
Codici prodotto
S26361-F3099-L828
10
Datasheet
Platforms based on the Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus
implement independent power planes for each system bus agent. As a result, the processor core
voltage (V
voltage (V
CC
) and system bus termination voltage (V
TT
) must connect to separate supplies. The
processor core voltage uses power delivery guidelines denoted by VRM 10.0 and the associated
load line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
10.0 Design Guidelines for further details).
load line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
10.0 Design Guidelines for further details).
The Low Voltage Intel Xeon processor with 800 MHz system bus uses a scalable system bus
protocol referred to as the “system bus” in this document. The system bus uses a split-transaction,
deferred reply protocol. The system bus uses Source-Synchronous Transfer (SST) of address and
data to improve performance. The processor transfers data four times per bus clock (4X data
transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two
times per bus clock and is referred to as a ‘double-clocked’ or the 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 6.4 GBytes/second (6400 MBytes/second). Finally, the
system bus is also used to deliver interrupts.
protocol referred to as the “system bus” in this document. The system bus uses a split-transaction,
deferred reply protocol. The system bus uses Source-Synchronous Transfer (SST) of address and
data to improve performance. The processor transfers data four times per bus clock (4X data
transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two
times per bus clock and is referred to as a ‘double-clocked’ or the 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 6.4 GBytes/second (6400 MBytes/second). Finally, the
system bus is also used to deliver interrupts.
The Low Voltage Intel Xeon processor with 800 MHz system bus also includes the Execute
Disable Bit capability previously available in Itanium
Disable Bit capability previously available in Itanium
®
processors. This feature combined with a
supported operating system allows memory to be marked as executable or non-executable. When
code attempts to run in non-executable memory, the processor raises an error to the operating
system. This feature can prevent some classes of viruses or worms that exploit buffer overrun
vulnerabilities and can thus help improve the overall security of the system. See the Intel
code attempts to run in non-executable memory, the processor raises an error to the operating
system. This feature can prevent some classes of viruses or worms that exploit buffer overrun
vulnerabilities and can thus help improve the overall security of the system. See the Intel
®
Architecture Software Developer’s Manual for more detailed information.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front side bus” or “System bus” refers to the interface between the processor, system core logic
(also known as the chipset components), and other bus agents. The system bus is a multiprocessing
interface to processors, memory, and I/O. For this document, “front side bus” or “system bus” are
used as generic terms for the “Low Voltage Intel
(also known as the chipset components), and other bus agents. The system bus is a multiprocessing
interface to processors, memory, and I/O. For this document, “front side bus” or “system bus” are
used as generic terms for the “Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus”.
Commonly used terms are explained here for clarification:
•
Low Voltage Intel
®
Xeon™ Processor with 800 MHz System Bus — Intel
®
32-bit
microprocessor intended for single/dual-processor applications. The Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus is based on Intel’s 90 nm process and will
include core frequency improvements, a large cache array, microarchitectural improvements
and additional instructions. The Low Voltage Intel Xeon processor with 800 MHz system bus
will use the mPGA604 socket. For this document, “processor” is used as the generic term for
the “Low Voltage Intel
include core frequency improvements, a large cache array, microarchitectural improvements
and additional instructions. The Low Voltage Intel Xeon processor with 800 MHz system bus
will use the mPGA604 socket. For this document, “processor” is used as the generic term for
the “Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus”.
•
Central Agent — The central agent is the host bridge to the processor and is typically known
as the chipset.
as the chipset.