Fujifilm Xeon S26361-F3099-L828 Scheda Tecnica
Codici prodotto
S26361-F3099-L828
Datasheet
13
2.0
Electrical Specifications
2.1
Power and Ground Pins
For clean on-chip power distribution, the processor has 181 V
CC
(power) and 185 V
SS
(ground)
inputs. All V
CC
pins must be connected to the processor power plane, while all V
SS
pins must be
connected to the system ground plane. The processor V
CC
pins must be supplied with the voltage
determined by the processor Voltage IDentification (VID) pins.
Eleven signals are denoted as V
TT
, which provide termination for the front side bus and power to
the I/O buffers. The platform must implement a separate supply for these pins, which meets the V
TT
specifications outlined in
.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus is capable of generating large average current swings
between low and full power states. This may cause voltages on power planes to sag below their
minimum values if bulk decoupling is not adequate. Larger bulk storage (C
between low and full power states. This may cause voltages on power planes to sag below their
minimum values if bulk decoupling is not adequate. Larger bulk storage (C
BULK
), such as
electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in
current demand by the component, such as coming out of an idle condition. Similarly, they act as a
storage well for current when entering an idle condition from a running condition. Care must be
taken in the baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in
current demand by the component, such as coming out of an idle condition. Similarly, they act as a
storage well for current when entering an idle condition from a running condition. Care must be
taken in the baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in
. Failure to do so can result in timing violations or reduced
lifetime of the component.
2.2.1
V
CC
Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and the baseboard designer must assure a low interconnect resistance from the voltage regulator
(VRD or VRM pins) to the mPGA604 socket. The power delivery solution must insure the voltage
and current specifications are met (defined in
and the baseboard designer must assure a low interconnect resistance from the voltage regulator
(VRD or VRM pins) to the mPGA604 socket. The power delivery solution must insure the voltage
and current specifications are met (defined in
).
2.2.2
V
TT
Decoupling
Decoupling must be provided on the baseboard. Decoupling solutions must be sized to meet the
expected load. To insure optimal performance, various factors associated with the power delivery
solution must be considered including regulator type, power plane and trace sizing, and component
placement. A conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors.
expected load. To insure optimal performance, various factors associated with the power delivery
solution must be considered including regulator type, power plane and trace sizing, and component
placement. A conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors.