Fujifilm Xeon S26361-F3099-L828 Scheda Tecnica
Codici prodotto
S26361-F3099-L828
Datasheet
85
8.0
Debug Tools Specifications
Please refer to the ITP700 Debug Port Design Guide for information regarding debug tool
specifications.
specifications.
provides collateral details.
8.1
Debug Port System Requirements
The Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus debug port is the command
and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of
the processors for system debug. The debug port, which is connected to the front side bus, is a
combination of the system, JTAG and execution signals. There are several mechanical, electrical
and functional constraints on the debug port that must be followed. The mechanical constraint
requires the debug port connector to be installed in the system with adequate physical clearance.
Electrical constraints exist due to the mixed high and low speed signals of the debug port for the
processor. While the JTAG signals operate at a maximum of 75 MHz, the execution signals operate
at the common clock front side bus frequency (200 MHz). The functional constraint requires the
debug port to use the JTAG system via a handshake and multiplexing scheme.
the processors for system debug. The debug port, which is connected to the front side bus, is a
combination of the system, JTAG and execution signals. There are several mechanical, electrical
and functional constraints on the debug port that must be followed. The mechanical constraint
requires the debug port connector to be installed in the system with adequate physical clearance.
Electrical constraints exist due to the mixed high and low speed signals of the debug port for the
processor. While the JTAG signals operate at a maximum of 75 MHz, the execution signals operate
at the common clock front side bus frequency (200 MHz). The functional constraint requires the
debug port to use the JTAG system via a handshake and multiplexing scheme.
In general, the information in this chapter may be used as a basis for including all run-control tools
in Low Voltage Intel
in Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus-based system designs,
including tools from vendors other than Intel.
Note:
The debug port and JTAG signal chain must be designed into the processor board in order to use
the ITP for debug purposes.
the ITP for debug purposes.
8.2
Target System Implementation
8.2.1
System Implementation
Specific connectivity and layout guidelines for the Debug Port are provided in the ITP700 Debug
Port Design Guide.
Port Design Guide.
8.3
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use
in debugging Low Voltage Intel
in debugging Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus systems. Tektronix*
and Agilent* should be contacted to obtain specific information about their logic analyzer
interfaces. The following information is general in nature. Specific information must be obtained
from the logic analyzer vendor.
interfaces. The following information is general in nature. Specific information must be obtained
from the logic analyzer vendor.
Due to the complexity of Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus-based
multiprocessor systems, the LAI is critical in providing the ability to probe and capture front side
bus signals. There are two sets of considerations to keep in mind when designing a Low Voltage
Intel
bus signals. There are two sets of considerations to keep in mind when designing a Low Voltage
Intel
®
Xeon™ processor with 800 MHz system bus-based system that can make use of an LAI:
mechanical and electrical.