Fujifilm Xeon 5060 S26361-F3318-L320 Scheda Tecnica
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S26361-F3318-L320
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
85
Thermal Specifications
If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will
immediately reduce its power consumption via modulation (starting and stopping) of
the internal core clock, independent of the processor temperature. When using On-
Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of
the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can
be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5%
increments. On-Demand mode may be used in conjunction with the Thermal Monitor;
however, if the system tries to enable On-Demand mode at the same time the TCC is
engaged, the factory configured duty cycle of the TCC will override the duty cycle
selected by the On-Demand mode.
immediately reduce its power consumption via modulation (starting and stopping) of
the internal core clock, independent of the processor temperature. When using On-
Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of
the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can
be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5%
increments. On-Demand mode may be used in conjunction with the Thermal Monitor;
however, if the system tries to enable On-Demand mode at the same time the TCC is
engaged, the factory configured duty cycle of the TCC will override the duty cycle
selected by the On-Demand mode.
6.2.3
PROCHOT# Signal
An external signal, PROCHOT# (processor hot) is asserted when the processor die
temperature of either processor cores has reached its factory configured trip point. If
Thermal Monitor is enabled (note that Thermal Monitor must be enabled for the
processor to be operating within specification), the TCC will be active when PROCHOT#
is asserted. The processor can be configured to generate an interrupt upon the
assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture Software
Developer’s Manual and the Conroe and Woodcrest Processor Family BIOS Writer’s
Guide for specific register and programming details.
temperature of either processor cores has reached its factory configured trip point. If
Thermal Monitor is enabled (note that Thermal Monitor must be enabled for the
processor to be operating within specification), the TCC will be active when PROCHOT#
is asserted. The processor can be configured to generate an interrupt upon the
assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture Software
Developer’s Manual and the Conroe and Woodcrest Processor Family BIOS Writer’s
Guide for specific register and programming details.
PROCHOT# is designed to assert at or a few degrees higher than maximum T
CASE
(as
specified by Thermal Profile A) when dissipating TDP power, and cannot be interpreted
as an indication of processor case temperature. This temperature delta accounts for
processor package, lifetime and manufacturing variations and attempts to ensure the
Thermal Control Circuit is not activated below maximum T
as an indication of processor case temperature. This temperature delta accounts for
processor package, lifetime and manufacturing variations and attempts to ensure the
Thermal Control Circuit is not activated below maximum T
CASE
when dissipating TDP
power. There is no defined or fixed correlation between the PROCHOT# trip
temperature, or the case temperature. Thermal solutions must be designed to the
processor specifications and cannot be adjusted based on experimental measurements
of T
temperature, or the case temperature. Thermal solutions must be designed to the
processor specifications and cannot be adjusted based on experimental measurements
of T
CASE
, or PROCHOT#.
6.2.4
FORCEPR# Signal
The FORCEPR# (force power reduction) input can be used by the platform to cause the
Dual-Core Intel
Dual-Core Intel
®
Xeon
®
Processor 5100 Series to activate the TCC. If the Thermal
Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR#
signal. Assertion of the FORCEPR# signal will activate TCC for both processor cores.
The TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an
asynchronous input. FORCEPR# can be used to thermally protect other system
components. To use the VR as an example, when FORCEPR# is asserted, the TCC
circuit in the processor will activate, reducing the current consumption of the processor
and the corresponding temperature of the VR.
signal. Assertion of the FORCEPR# signal will activate TCC for both processor cores.
The TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an
asynchronous input. FORCEPR# can be used to thermally protect other system
components. To use the VR as an example, when FORCEPR# is asserted, the TCC
circuit in the processor will activate, reducing the current consumption of the processor
and the corresponding temperature of the VR.
It should be noted that assertion of FORCEPR# does not automatically assert
PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high
temperature situation is detected. A minimum pulse width of 500
PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high
temperature situation is detected. A minimum pulse width of 500
µ
s is recommended
when FORCEPR# is asserted by the system. Sustained activation of the FORCEPR#
signal may cause noticeable platform performance degradation.
signal may cause noticeable platform performance degradation.
Refer to the appropriate platform design guidelines for details on implementing the
FORCEPR# signal feature.
FORCEPR# signal feature.