Texas Instruments CDCLVD2102EVM - CDCLVD2102 Evaluation Module CDCLVD2102EVM CDCLVD2102EVM Scheda Tecnica
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CDCLVD2102EVM
User's Guide
SCAU043 – June 2010
Low-Additive Jitter, Four LVDS Outputs Clock Buffer
Evaluation Board
This user's guide describes how to use the CDCLVD1204/CDCLVD2102 evaluation module (EVM) and
provides users with guidelines to build their own systems. The EVM schematics and bill of materials are
included.
provides users with guidelines to build their own systems. The EVM schematics and bill of materials are
included.
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Features
Figure 1. CDCLVD1204/CDCLVD2102 Evaluation Board
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Easy-to-use evaluation board to fan out low-phase noise clocks
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Easy device setup
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Fast configuration
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Control pins configurable through jumpers
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Board powered at 2.5 V
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Single-ended or differential input clocks
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Device supports four LVDS outputs, EVM supports two LVDS outputs
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General Description
The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have two
universal input buffers that support single-ended or differential clock inputs and are selectable through a
control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can provide the
LVDS common-mode voltage to the device inputs.
universal input buffers that support single-ended or differential clock inputs and are selectable through a
control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can provide the
LVDS common-mode voltage to the device inputs.
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SCAU043 – June 2010
Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board
Copyright © 2010, Texas Instruments Incorporated