Microchip Technology IC PIC MCU PIC16F1937-I/PT TQFP-44 MCP PIC16F1937-I/PT Scheda Tecnica
Codici prodotto
PIC16F1937-I/PT
2008-2011 Microchip Technology Inc.
DS41364E-page 269
PIC16(L)F1934/6/7
24.5.8
GENERAL CALL ADDRESS
SUPPORT
SUPPORT
The addressing procedure for the I
2
C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an Acknowledge.
The general call address is a reserved address in the
I
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an Acknowledge.
The general call address is a reserved address in the
I
2
C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
shows a general call reception
sequence.
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
FIGURE 24-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
24.5.9
SSP MASK REGISTER
An SSP Mask (SSPMSK) register (
) is
available in I
2
C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
reception of the first (high) byte of the address.
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
R/W =
0
ACK
General Call Address
Address is compared to General Call Address
Receiving Data
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
after ACK, set interrupt
GCEN (SSPCON2<7>)
’1’