Scheda Tecnica (PIC16F1937-I/PT)SommarioDevices Included In This Data Sheet:3High-Performance RISC CPU:3Special Microcontroller Features:3PIC16LF193X Low-Power Features:3Peripheral Features:3Peripheral Features (Continued):4PIC16(L)F193X Family Types4Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16(L)F1936)5Pin Diagram – 28-Pin QFN/UQFN (PIC16(L)F1936)6TABLE 1: 28-Pin Summary (PIC16(L)F1936)7Pin Diagram – 40-Pin PDIP (PIC16(L)F1934/7)8Pin Diagram – 40-Pin UQFN 5x5 (PIC16(L)F1934/7)9Pin Diagram – 44-Pin QFN (PIC16(L)F1934/7)10Pin Diagram – 44-Pin TQFP (PIC16(L)F1934/7)11TABLE 2: 40/44-Pin Summary(PIC16(L)F1934/7)12Table of Contents13Most Current Data Sheet14Errata14Customer Notification System141.0 Device Overview15TABLE 1-1: Device Peripheral Summary15FIGURE 1-1: PIC16(L)F1934/6/7 Block Diagram16TABLE 1-2: PIC16(L)F1934/6/7 Pinout Description172.0 Enhanced Mid-range CPU232.1 Automatic Interrupt Context Saving232.2 16-level Stack with Overflow and Underflow232.3 File Select Registers232.4 Instruction Set23FIGURE 2-1: Core Block Diagram243.0 Memory Organization253.1 Program Memory Organization25TABLE 3-1: Device Sizes and Addresses25FIGURE 3-1: Program Memory Map And Stack For 4KW parts26FIGURE 3-2: Program Memory Map And Stack For 8KW parts263.1.1 Reading Program Memory as Data27EXAMPLE 3-1: RETLW Instruction27EXAMPLE 3-2: Accessing Program Memory Via FSR283.2 Data Memory Organization283.2.1 Core Registers28Register 3-1: STATUS: STATUS Register293.2.2 Special Function Register303.2.3 General Purpose RAM303.2.4 Common RAM30FIGURE 3-3: Banked Memory Partitioning303.2.5 Device Memory Maps30TABLE 3-2: Memory Map Tables30TABLE 3-3: PIC16(L)F1934 Memory Map, Banks 0-731TABLE 3-4: PIC16(L)F1934 Memory Map, Banks 8-1532TABLE 3-5: PIC16(L)F1936/1937 Memory Map, Banks 0-733TABLE 3-6: PIC16(L)F1936/1937 Memory Map, Banks 8-1534TABLE 3-7: PIC16(L)F1934/6/7 Memory Map, Banks 16-2335TABLE 3-8: PIC16(L)F1934/6/7 Memory Map, Banks 24-3136TABLE 3-9: PIC16(L)F1936 Memory Map, Bank 1537TABLE 3-10: PIC16(L)F1934/7 Memory Map, Bank 1537TABLE 3-11: PIC16(L)F1934/6/7 Memory Map, Bank 31383.2.6 Special Function Registers Summary38TABLE 3-12: Special Function Register Summary393.3 PCL and PCLATH53FIGURE 3-4: Loading Of PC In Different Situations533.3.1 Modifying PCL533.3.2 computed goto533.3.3 Computed Function Calls533.3.4 Branching533.4 Stack543.4.1 Accessing the Stack54FIGURE 3-5: Accessing the Stack Example 154FIGURE 3-6: Accessing the Stack Example 255FIGURE 3-7: Accessing the Stack Example 355FIGURE 3-8: Accessing the Stack Example 4563.4.2 Overflow/Underflow Reset563.5 Indirect Addressing56FIGURE 3-9: Indirect Addressing573.5.1 Traditional Data Memory58FIGURE 3-10: Traditional Data Memory Map583.5.2 Linear Data Memory59FIGURE 3-11: Linear Data Memory Map593.5.3 Program Flash Memory59FIGURE 3-12: Program Flash Memory Map594.0 Device Configuration614.1 Configuration Words61Register 4-1: Configuration Word 162Register 4-2: Configuration Word 2644.2 Code Protection654.2.1 Program Memory Protection654.2.2 Data EEPROM Protection654.3 Write Protection654.4 User ID654.5 Device ID and Revision ID66Register 4-3: DEVICEID: Device ID Register(1)665.0 Oscillator Module (With Fail-Safe Clock Monitor)675.1 Overview67FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram685.2 Clock Source Types695.2.1 External Clock Sources69FIGURE 5-2: External Clock (EC) Mode Operation69FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)70FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)70FIGURE 5-5: Quartz Crystal Operation (Timer1 Oscillator)71FIGURE 5-6: External RC Modes715.2.2 Internal Clock Sources72FIGURE 5-7: Internal Oscillator Switch Timing755.3 Clock Switching765.3.1 System Clock Select (SCS) BitS765.3.2 Oscillator Start-up Time-out Status (OSTS) Bit765.3.3 Timer1 Oscillator765.3.4 Timer1 Oscillator Ready (T1OSCR) Bit765.4 Two-Speed Clock Start-up Mode775.4.1 Two-Speed Start-up Mode Configuration77TABLE 5-1: Oscillator Switching Delays775.4.2 Two-speed Start-up Sequence785.4.3 Checking Two-Speed Clock Status78FIGURE 5-8: Two-Speed Start-up785.5 Fail-Safe Clock Monitor79FIGURE 5-9: FSCM Block Diagram795.5.1 Fail-Safe Detection795.5.2 Fail-Safe Operation795.5.3 Fail-Safe Condition Clearing795.5.4 Reset or Wake-up from Sleep79FIGURE 5-10: FSCM Timing Diagram805.6 Oscillator Control Registers81Register 5-1: OSCCON: Oscillator Control Register81Register 5-2: OSCSTAT: Oscillator Status Register82Register 5-3: OSCTUNE: Oscillator Tuning Register83TABLE 5-2: Summary of Registers Associated with Clock Sources83TABLE 5-3: Summary of cONFIGURATION wORD with Clock Sources836.0 Resets85FIGURE 6-1: Simplified Block Diagram Of On-Chip Reset Circuit856.1 Power-on Reset (POR)866.1.1 Power-up Timer (PWRT)866.2 Brown-Out Reset (BOR)86TABLE 6-1: BOR Operating Modes866.2.1 BOR is Always On866.2.2 BOR is Off in Sleep866.2.3 BOR Controlled by Software86FIGURE 6-2: Brown-Out Situations87Register 6-1: BORCON: Brown-out Reset Control Register876.3 MCLR88TABLE 6-2: MCLR Configuration886.3.1 MCLR Enabled886.3.2 MCLR Disabled886.4 Watchdog Timer (WDT) Reset886.5 RESET Instruction886.6 Stack Overflow/Underflow Reset886.7 Programming Mode Exit886.8 Power-Up Timer886.9 Start-up Sequence88FIGURE 6-3: Reset Start-Up Sequence896.10 Determining the Cause of a Reset90TABLE 6-3: Reset Status Bits and Their Significance90TABLE 6-4: Reset Condition for Special Registers(2)906.11 Power Control (PCON) Register91Register 6-2: PCON: Power Control Register91TABLE 6-5: Summary Of Registers Associated With Resets927.0 Interrupts93FIGURE 7-1: Interrupt Logic937.1 Operation947.2 Interrupt Latency94FIGURE 7-2: Interrupt Latency95FIGURE 7-3: INT Pin Interrupt Timing967.3 Interrupts During Sleep977.4 INT Pin977.5 Automatic Context Saving977.6 Interrupt Control Registers987.6.1 INTCON Register98Register 7-1: INTCON: Interrupt Control Register987.6.2 PIE1 Register99Register 7-2: PIE1: Peripheral Interrupt Enable Register 1997.6.3 PIE2 Register100Register 7-3: PIE2: Peripheral Interrupt Enable Register 21007.6.4 PIE3 Register101Register 7-4: PIE3: Peripheral Interrupt Enable Register 31017.6.5 PIR1 Register102Register 7-5: PIR1: Peripheral Interrupt Request Register 11027.6.6 PIR2 Register103Register 7-6: PIR2: Peripheral Interrupt Request Register 21037.6.7 PIR3 Register104Register 7-7: PIR3: Peripheral Interrupt Request Register 3104TABLE 7-1: Summary of Registers Associated with Interrupts1058.0 Low Dropout (LDO) Voltage Regulator107TABLE 8-1: VCAPEN<1:0> Select Bits107TABLE 8-2: Summary of cONFIGURATION wORD with LDO1079.0 Power-Down Mode (Sleep)1099.1 Wake-up from Sleep1099.1.1 Wake-up Using Interrupts110FIGURE 9-1: Wake-Up From Sleep Through Interrupt110TABLE 9-1: Summary of Registers Associated with pOWER-dOWN mODE11010.0 Watchdog Timer111FIGURE 10-1: Watchdog Timer Block Diagram11110.1 Independent Clock Source11210.2 WDT Operating Modes11210.2.1 WDT Is Always On11210.2.2 WDT Is Off In Sleep11210.2.3 WDT Controlled By Software112TABLE 10-1: WDT Operating Modes11210.3 Time-Out Period11210.4 Clearing the WDT11210.5 Operation During Sleep112TABLE 10-2: WDT Clearing Conditions11210.6 Watchdog Control Register113Register 10-1: WDTCON: Watchdog Timer Control Register113TABLE 10-3: Summary of Registers Associated with Watchdog Timer114TABLE 10-4: Summary of cONFIGURATION wORD with Watchdog Timer11411.0 Data EEPROM and Flash Program Memory Control11511.1 EEADRL and EEADRH Registers11511.1.1 EECON1 and EECON2 Registers11511.2 Using the Data EEPROM11611.2.1 Reading the Data EEPROM Memory116EXAMPLE 11-1: Data EEPROM Read11611.2.2 Writing to the Data EEPROM Memory11611.2.3 Protection Against Spurious Write11611.2.4 Data EEPROM Operation During Code-Protect116EXAMPLE 11-2: Data EEPROM Write117FIGURE 11-1: Flash Program Memory Read Cycle Execution11711.3 Flash Program Memory Overview118TABLE 11-1: Flash Memory Organization By Device11811.3.1 Reading the Flash Program Memory118EXAMPLE 11-3: FLASH PROGRAM MEMORY Read11911.3.2 Erasing Flash Program Memory12011.3.3 Writing to Flash Program Memory120FIGURE 11-2: Block WRITES to Flash Program Memory With 8 write latches121EXAMPLE 11-4: Erasing One Row of Program Memory -122EXAMPLE 11-5: Writing to Flash Program Memory12311.4 Modifying Flash Program Memory12411.5 User ID, Device ID and Configuration Word Access124TABLE 11-2: User ID, Device ID and Configuration Word Access (cfgs = 1)12411.6 Write Verify125EXAMPLE 11-6: EEPROM Write Verify125Register 11-1: EEDATL: EEPROM Data Low Byte Register126Register 11-2: EEDATH: EEPROM Data hIGH bYTE Register126Register 11-3: EEADRL: EEPROM Address Low Byte Register126Register 11-4: EEADRH: EEPROM Address hIGH bYTE Register126Register 11-5: EECON1: EEPROM Control 1 Register127Register 11-6: EECON2: EEPROM Control 2 Register128TABLE 11-3: Summary of Registers Associated with Data EEPROM12812.0 I/O Ports129TABLE 12-1: Port Availability Per Device129FIGURE 12-1: Generic I/O Port Operation129EXAMPLE 12-1: Initializing PORTA12912.1 Alternate Pin Function130Register 12-1: APFCON: Alternate Pin Function Control Register13112.2 PORTA Registers13212.2.1 ANSELA Register13212.2.2 PORTA Functions and Output Priorities132TABLE 12-2: PORTA Output Priority132Register 12-2: PORTA: PORTA Register133Register 12-3: TRISA: PORTA Tri-State Register133Register 12-4: LATA: PORTA Data Latch Register133Register 12-5: ANSELA: PORTA Analog Select Register134TABLE 12-3: Summary of Registers Associated with PORTA135TABLE 12-4: Summary of cONFIGURATION wORD with PORTA13512.3 PORTB Registers13612.3.1 Weak Pull-Ups13612.3.2 Interrupt-on-Change13612.3.3 ANSELB Register13612.3.4 PORTB Functions and Output Priorities137TABLE 12-5: PORTB Output Priority137Register 12-6: PORTB: PORTB Register138Register 12-7: TRISB: PORTB Tri-State Register138Register 12-8: LATB: PORTB Data Latch Register138Register 12-9: ANSELB: PORTB Analog Select Register139Register 12-10: WPUB: WEAK PULL-uP PORTB REGISTER139TABLE 12-6: Summary of Registers Associated with PORTB14012.4 PORTC Registers14112.4.1 PORTC Functions and Output Priorities141TABLE 12-7: PORTC Output Priority141Register 12-11: PORTC: PORTC Register142Register 12-12: TRISC: PORTC Tri-State Register142Register 12-13: LATC: PORTC Data Latch Register142TABLE 12-8: Summary of Registers Associated with PORTC14312.5 PORTD Registers14412.5.1 ANSELD Register14412.5.2 PORTD Functions and Output Priorities144TABLE 12-9: PORTD Output Priority144Register 12-14: PORTD: PORTD Register(1)145Register 12-15: TRISD: PORTD Tri-State Register(1)145Register 12-16: LATD: PORTD Data Latch Register145Register 12-17: ANSELD: PORTD Analog Select Register(2)146TABLE 12-10: Summary of Registers Associated with PORTD(1)14612.6 PORTE Registers14712.6.1 ANSELE Register14712.6.2 PORTE Functions and Output Priorities147TABLE 12-11: PORTE Output Priority147Register 12-18: PORTE: PORTE Register148Register 12-19: TRISE: PORTE Tri-State Register148Register 12-20: LATE: PORTE Data Latch Register149Register 12-21: ANSELE: PORTE Analog Select Register149Register 12-22: WPUE: WEAK PULL-uP PORTe REGISTER150TABLE 12-12: Summary of Registers Associated with PORTE15013.0 Interrupt-On-Change15113.1 Enabling the Module15113.2 Individual Pin Configuration15113.3 Interrupt Flags15113.4 Clearing Interrupt Flags151EXAMPLE 13-1:15113.5 Operation in Sleep151FIGURE 13-1: Interrupt-On-Change Block Diagram15113.6 Interrupt-On-Change Registers152Register 13-1: IOCBP: Interrupt-on-Change Positive Edge Register152Register 13-2: IOCBN: Interrupt-on-Change Negative Edge Register152Register 13-3: IOCBF: Interrupt-on-Change Flag Register152TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change15314.0 Fixed Voltage Reference (FVR)15514.1 Independent Gain Amplifiers15514.2 FVR Stabilization Period155FIGURE 14-1: Voltage Reference Block Diagram15514.3 FVR Control Registers156Register 14-1: FVRCON: Fixed Voltage Reference Control Register156TABLE 14-1: Summary of Registers Associated with Fixed Voltage Reference15615.0 Analog-to-Digital Converter (ADC) Module157FIGURE 15-1: ADC Block Diagram15715.1 ADC Configuration15815.1.1 Port Configuration15815.1.2 Channel Selection15815.1.3 ADC Voltage Reference15815.1.4 Conversion Clock158TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies159FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles15915.1.5 Interrupts16015.1.6 Result Formatting160FIGURE 15-3: 10-Bit A/D Conversion Result Format16015.2 ADC Operation16115.2.1 Starting a Conversion16115.2.2 Completion of a Conversion16115.2.3 Terminating a conversion16115.2.4 ADC Operation During Sleep16115.2.5 Special Event Trigger161TABLE 15-2: Special Event Trigger16115.2.6 A/D Conversion Procedure162EXAMPLE 15-1: A/D Conversion16215.2.7 ADC Register Definitions163Register 15-1: ADCON0: A/D Control Register 0163Register 15-2: ADCON1: A/D Control Register 1164Register 15-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0165Register 15-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0165Register 15-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1166Register 15-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 116615.3 A/D Acquisition Requirements167EQUATION 15-1: Acquisition Time Example167FIGURE 15-4: Analog Input Model168FIGURE 15-5: ADC Transfer Function168TABLE 15-3: Summary of Registers Associated with ADC16916.0 Temperature Indicator Module17116.1 Circuit Operation171EQUATION 16-1: Vout Ranges171FIGURE 16-1: Temperature Circuit Diagram17116.2 Minimum Operating Vdd vs. Minimum Sensing Temperature171TABLE 16-1: Recommended Vdd vs. Range17116.3 Temperature Output17116.4 ADC Acquisition Time17117.0 Digital-to-Analog Converter (DAC) Module17317.1 Output Voltage Selection173EQUATION 17-1: DAC Output Voltage17317.2 Ratiometric Output Level17317.3 DAC Voltage Reference Output173FIGURE 17-1: Digital-to-Analog Converter Block Diagram174FIGURE 17-2: Voltage Reference Output Buffer Example17417.4 Low-Power Voltage State17517.4.1 Output Clamped to Positive Voltage Source17517.4.2 Output Clamped to Negative Voltage Source175FIGURE 17-3: Output Voltage Clamping Examples17517.5 Operation During Sleep17517.6 Effects of a Reset175Register 17-1: DACCON0: Voltage Reference Control Register 0176Register 17-2: DACCON1: Voltage Reference Control Register 1176TABLE 17-1: Summary of Registers Associated with the DAC Module17618.0 Comparator Module17718.1 Comparator Overview177FIGURE 18-1: Single Comparator177FIGURE 18-2: Comparator Module Simplified Block Diagram17818.2 Comparator Control17918.2.1 Comparator Enable17918.2.2 Comparator Output Selection17918.2.3 Comparator Output Polarity179TABLE 18-1: Comparator Output State vs. Input Conditions17918.2.4 Comparator Speed/Power Selection17918.3 Comparator Hysteresis18018.4 Timer1 Gate Operation18018.4.1 Comparator Output Synchronization18018.5 Comparator Interrupt18018.6 Comparator Positive Input Selection18018.7 Comparator Negative Input Selection18118.8 Comparator Response Time18118.9 Interaction with ECCP Logic18118.10 Analog Input Connection Considerations181FIGURE 18-3: Analog Input Model182Register 18-1: CMxCON0: Comparator X Control Register 0183Register 18-2: CMxCON1: Comparator Cx Control Register 1184Register 18-3: CMOUT: Comparator Output Register184TABLE 18-2: Summary of Registers Associated with Comparator Module18519.0 SR Latch18719.1 Latch Operation18719.2 Latch Output18719.3 Effects of a Reset187FIGURE 19-1: SR Latch Simplified Block Diagram188TABLE 19-1: SRCLK Frequency table189Register 19-1: SRCON0: SR Latch Control 0 Register189Register 19-2: SRCON1: SR Latch Control 1 Register190TABLE 19-2: Summary of Registers Associated with SR Latch Module19020.0 Timer0 Module19120.1 Timer0 Operation19120.1.1 8-bit Timer mode19120.1.2 8-Bit Counter Mode191FIGURE 20-1: Block Diagram of the Timer019120.1.3 Software Programmable Prescaler19220.1.4 Timer0 Interrupt19220.1.5 8-BIT COUNTER MODE SYNCHRONIZATION19220.1.6 Operation During Sleep19220.2 Option and Timer0 Control Register193Register 20-1: OPTION_REG: OPTION Register193TABLE 20-1: Summary of Registers Associated with Timer019321.0 Timer1 Module with Gate Control195FIGURE 21-1: Timer1 Block Diagram19521.1 Timer1 Operation196TABLE 21-1: Timer1 Enable Selections19621.2 Clock Source Selection19621.2.1 Internal Clock Source19621.2.2 External Clock Source196TABLE 21-2: Clock Source Selections19621.3 Timer1 Prescaler19721.4 Timer1 Oscillator19721.5 Timer1 Operation in Asynchronous Counter Mode19721.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode19721.6 Timer1 Gate19721.6.1 Timer1 Gate Enable197TABLE 21-3: Timer1 Gate Enable Selections19721.6.2 Timer1 Gate Source Selection198TABLE 21-4: Timer1 Gate Sources19821.6.3 Timer1 Gate Toggle Mode19821.6.4 Timer1 Gate Single-Pulse Mode19821.6.5 Timer1 Gate Value Status19821.6.6 Timer1 Gate Event Interrupt19821.7 Timer1 Interrupt19921.8 Timer1 Operation During Sleep19921.9 ECCP/CCP Capture/Compare Time Base19921.10 ECCP/CCP Special Event Trigger199FIGURE 21-2: Timer1 Incrementing Edge199FIGURE 21-3: Timer1 Gate Enable Mode200FIGURE 21-4: Timer1 Gate Toggle Mode200FIGURE 21-5: Timer1 Gate Single-Pulse Mode201FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode20221.11 Timer1 Control Register203Register 21-1: T1CON: Timer1 Control Register20321.12 Timer1 Gate Control Register204Register 21-2: T1GCON: Timer1 Gate Control Register204TABLE 21-5: Summary of Registers Associated with Timer120522.0 Timer2/4/6 Modules207FIGURE 22-1: Timer2/4/6 Block Diagram20722.1 Timer2/4/6 Operation20822.2 Timer2/4/6 Interrupt20822.3 Timer2/4/6 Output20822.4 Timer2/4/6 Operation During Sleep20822.5 Timer2/4/6 Control Register209Register 22-1: TxCON: Timer2/timer4/timer6 Control Register209TABLE 22-1: Summary of Registers Associated With Timer2/4/621023.0 Capture/Compare/PWM Modules211TABLE 23-1: PWM Resources21123.1 Capture Mode21223.1.1 CCP pin Configuration212FIGURE 23-1: Capture Mode Operation Block Diagram21223.1.2 Timer1 Mode Resource21223.1.3 Software Interrupt Mode21223.1.4 CCP Prescaler212EXAMPLE 23-1: Changing Between Capture Prescalers21223.1.5 Capture During Sleep21223.1.6 Alternate Pin Locations213TABLE 23-2: Summary of Registers Associated with Capture21323.2 Compare Mode214FIGURE 23-2: Compare Mode Operation Block Diagram21423.2.1 CCP Pin Configuration21423.2.2 timer1 Mode Resource21423.2.3 Software Interrupt Mode21423.2.4 Special Event Trigger214TABLE 23-3: Special Event Trigger21423.2.5 Compare During Sleep21523.2.6 Alternate Pin Locations215TABLE 23-4: Summary of Registers Associated with cOMPARE21523.3 PWM Overview21623.3.1 Standard PWM Operation216FIGURE 23-3: CCP PWM Output Signal216FIGURE 23-4: Simplified PWM Block Diagram21623.3.2 Setup for PWM Operation21723.3.3 Timer2/4/6 Timer Resource21723.3.4 PWM period217EQUATION 23-1: PWM Period21723.3.5 PWM Duty Cycle217EQUATION 23-2: Pulse Width217EQUATION 23-3: Duty Cycle Ratio21723.3.6 PWM Resolution218EQUATION 23-4: PWM Resolution218TABLE 23-5: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)218TABLE 23-6: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)218TABLE 23-7: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)21823.3.7 Operation in Sleep Mode21923.3.8 Changes in System Clock Frequency21923.3.9 Effects of Reset21923.3.10 Alternate Pin Locations219TABLE 23-8: Summary of Registers Associated with Standard PWM21923.4 PWM (Enhanced Mode)220FIGURE 23-5: Example Simplified Block Diagram of the Enhanced PWM Mode220TABLE 23-9: Example Pin Assignments for Various PWM Enhanced Modes221FIGURE 23-6: Example PWM (enhanced Mode) Output Relationships (Active-High State)221FIGURE 23-7: Example Enhanced PWM Output Relationships (Active-Low State)22223.4.1 Half-Bridge Mode223FIGURE 23-8: Example of Half-Bridge PWM Output223FIGURE 23-9: Example of Half-Bridge Applications22323.4.2 Full-Bridge Mode224FIGURE 23-10: Example of Full-Bridge Application224FIGURE 23-11: Example of Full-Bridge PWM Output225FIGURE 23-12: Example of PWM Direction Change226FIGURE 23-13: Example of PWM Direction Change at Near 100% Duty Cycle22723.4.3 Enhanced PWM Auto-shutdown mode228FIGURE 23-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)22823.4.4 Auto-Restart Mode229FIGURE 23-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)22923.4.5 Programmable Dead-Band Delay Mode230FIGURE 23-16: Example of Half-Bridge PWM Output230FIGURE 23-17: Example of Half-Bridge Applications23023.4.6 PWM Steering Mode231FIGURE 23-18: Simplified Steering Block Diagram23123.4.7 Start-up Considerations232FIGURE 23-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)232FIGURE 23-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)232TABLE 23-10: Summary of Registers Associated with Enhanced PWM23323.5 CCP Control Register234Register 23-1: CCPXCON: CCPx Control Register234Register 23-2: CCPTMRS0: PWM Timer Selection Control Register 0235Register 23-3: CCPTMRS1: PWM Timer Selection Control Register 1235Register 23-4: CCPxAS: CCPx Auto-Shutdown Control Register236Register 23-5: PWMxCON: Enhanced PWM Control Register237Register 23-6: PSTRxCON: PWM Steering Control Register(1)23824.0 Master Synchronous Serial Port Module23924.1 Master SSP (MSSP) Module Overview239FIGURE 24-1: MSSP Block Diagram (SPI mode)239FIGURE 24-2: MSSP Block Diagram (I2C™ Master mode)240FIGURE 24-3: MSSP Block Diagram (I2C™ Slave mode)24124.2 SPI Mode Overview242FIGURE 24-4: SPI Master and Multiple Slave Connection24324.2.1 SPI Mode ReGISTERS24324.2.2 spi mODE oPERATION244FIGURE 24-5: SPI Master/Slave Connection24424.2.3 SPI Master Mode245FIGURE 24-6: SPI Mode Waveform (Master Mode)24524.2.4 SPI SLAVE MODE24624.2.5 SLAVE SELECT SYNCHRONIZATION246FIGURE 24-7: SPI Daisy-Chain Connection247FIGURE 24-8: slave Select Synchronous Waveform247FIGURE 24-9: SPI Mode Waveform (Slave Mode With CKE = 0)248FIGURE 24-10: SPI Mode Waveform (SLAve Mode With CKE = 1)24824.2.6 SPI OPERATION IN Sleep MODE249TABLE 24-1: Summary of Registers Associated with SPI Operation24924.3 I2C Mode Overview250FIGURE 24-11: I2C Master/ Slave Connection25024.3.1 CLOCK STRETCHING25124.3.2 ARBITRATION25124.4 I2C™ Mode Operation25124.4.1 Byte Format25124.4.2 Definition of I2C terminology25124.4.3 SDA and SCL PINS25124.4.4 SDA Hold Time251TABLE 24-2: I2C Bus terms25224.4.5 Start Condition25224.4.6 STOP condition25224.4.7 Restart condition25224.4.8 START/STOP Condition Interrupt masking252FIGURE 24-12: I2C START and STOP Conditions253FIGURE 24-13: I2C Restart Condition25324.4.9 Acknowledge Sequence25424.5 I2C Slave Mode Operation25424.5.1 slave mode addresses25424.5.2 Slave Reception255FIGURE 24-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)256FIGURE 24-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)257FIGURE 24-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)258FIGURE 24-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)25924.5.3 SLAVE Transmission260FIGURE 24-18: I2C Slave, 7-Bit Address, TRANSMISSION (AHEN = 0)261FIGURE 24-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)26324.5.4 Slave mode 10-bit Address Reception26424.5.5 10-bit Addressing With Address Or Data Hold264FIGURE 24-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)265FIGURE 24-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)266FIGURE 24-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)26724.5.6 Clock Stretching26824.5.7 Clock Synchronization and the CKP bit268FIGURE 24-23: Clock Synchronization Timing26824.5.8 General call address support269FIGURE 24-24: SLAVE MODE GENERAl call address sequence26924.5.9 SSP Mask Register26924.6 I2C Master Mode27024.6.1 I2C Master Mode Operation27024.6.2 Clock Arbitration271FIGURE 24-25: Baud Rate Generator Timing with Clock Arbitration27124.6.3 WCOL Status Flag27124.6.4 I2C Master Mode Start Condition Timing272FIGURE 24-26: First Start Bit Timing27224.6.5 I2C Master Mode REPEATED Start Condition Timing273FIGURE 24-27: Repeat Start Condition Waveform27324.6.6 I2C Master Mode Transmission274FIGURE 24-28: I2C Master Mode Waveform (Reception, 7-Bit Address)27524.6.7 I2C Master Mode Reception276FIGURE 24-29: I2C Master Mode Waveform (Reception, 7-Bit Address)27724.6.8 Acknowledge Sequence Timing27824.6.9 Stop Condition Timing278FIGURE 24-30: Acknowledge Sequence Waveform278FIGURE 24-31: Stop Condition Receive or Transmit Mode27824.6.10 Sleep Operation27924.6.11 Effects of a Reset27924.6.12 Multi-Master Mode27924.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration279FIGURE 24-32: Bus Collision Timing for Transmit and Acknowledge279FIGURE 24-33: Bus Collision During Start Condition (SDA Only)280FIGURE 24-34: Bus Collision During Start Condition (SCL = 0)281FIGURE 24-35: BRG Reset Due to Sda Arbitration During Start Condition281FIGURE 24-36: Bus Collision During a Repeated Start Condition (Case 1)282FIGURE 24-37: Bus Collision During Repeated Start Condition (Case 2)282FIGURE 24-38: Bus Collision During a Stop Condition (Case 1)283FIGURE 24-39: Bus Collision During a Stop Condition (Case 2)283TABLE 24-3: Summary of Registers Associated with I2C™ Operation28424.7 Baud Rate Generator285FIGURE 24-40: Baud Rate Generator Block Diagram285TABLE 24-4: MSSP Clock Rate w/BRG285Register 24-1: SSPSTAT: SSP STATUS Register286Register 24-2: SSPCON1: SSP Control Register 1287Register 24-3: SSPCON2: SSP Control Register 2288Register 24-4: SSPCON3: SSP Control Register 3289Register 24-5: SSPMSK: SSP Mask Register290Register 24-6: SSPADD: MSSP Address and Baud Rate Register (I2C Mode)29025.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)291FIGURE 25-1: EUSART Transmit Block Diagram291FIGURE 25-2: EUSART Receive Block Diagram29225.1 EUSART Asynchronous Mode29325.1.1 EUSART Asynchronous Transmitter293FIGURE 25-3: Asynchronous Transmission294FIGURE 25-4: Asynchronous Transmission (Back-to-Back)294TABLE 25-1: Summary of Registers Associated with Asynchronous Transmission29525.1.2 EUSART Asynchronous Receiver296FIGURE 25-5: Asynchronous Reception298TABLE 25-2: Summary of Registers Associated with Asynchronous Reception29925.2 Clock Accuracy with Asynchronous Operation300Register 25-1: TXSTA: Transmit STATUS AND CONTROL REGISTER300Register 25-2: RCSTA: Receive STATUS AND CONTROL REGISTER(1)301Register 25-3: BAUDCON: BAUD RATE CONTROL REGISTER30225.3 EUSART Baud Rate Generator (BRG)303EXAMPLE 25-1: Calculating Baud Rate Error303TABLE 25-3: Baud Rate Formulas304TABLE 25-4: Summary of Registers Associated with the bAUD rATE gENERATOR304TABLE 25-5: BAUD Rates for Asynchronous Modes30525.3.1 Auto-Baud Detect308TABLE 25-6: BRG Counter Clock Rates308FIGURE 25-6: Automatic Baud Rate Calibration30825.3.2 Auto-baud Overflow30925.3.3 Auto-Wake-up on Break309FIGURE 25-7: Auto-Wake-up bit (WUE) timing during normal operation310FIGURE 25-8: Auto-Wake-up bit (WUE) timings during Sleep31025.3.4 BREAK Character Sequence31125.3.5 Receiving a BREAK Character311FIGURE 25-9: Send Break Character Sequence31125.4 EUSART Synchronous Mode31225.4.1 Synchronous Master Mode312FIGURE 25-10: Synchronous Transmission313FIGURE 25-11: Synchronous Transmission (Through TXEN)313TABLE 25-7: Summary of Registers Associated with Synchronous Master Transmission313FIGURE 25-12: Synchronous Reception (Master Mode, SREN)315TABLE 25-8: Summary of Registers Associated with Synchronous Master Reception31525.4.2 Synchronous slave Mode316TABLE 25-9: Summary of Registers Associated with Synchronous Slave Transmission316TABLE 25-10: Summary of Registers Associated with Synchronous Slave Reception31725.5 EUSART Operation During Sleep31825.5.1 Synchronous Receive During Sleep31825.5.2 Synchronous Transmit During Sleep31826.0 Capacitive Sensing (CPS) Module319FIGURE 26-1: Capacitive Sensing Block Diagram31926.1 Analog MUX32026.2 Capacitive Sensing Oscillator32026.3 Voltage References32026.4 Power Ranges320TABLE 26-1: Power Range Selection32026.5 Timer Resources32126.6 Fixed Time Base32126.6.1 Timer032126.6.2 Timer1321TABLE 26-2: TIMER1 ENABLE FUNCTION32126.7 Software Control32126.7.1 Nominal Frequency (No Capacitive Load)32126.7.2 Reduced Frequency (additional capacitive load)32126.7.3 Frequency threshold32226.8 Operation during Sleep322Register 26-1: CPSCON0: Capacitive Sensing Control Register 0323Register 26-2: CPSCON1: Capacitive Sensing Control Register 1324TABLE 26-3: Summary of Registers Associated with Capacitive Sensing32527.0 Liquid Crystal Display (LCD) Driver Module327FIGURE 27-1: LCD Driver Module Block Diagram32727.1 LCD Registers328TABLE 27-1: LCD Segment and Data Registers328Register 27-1: LCDCON: Liquid Crystal Display (LCD) Control Register329Register 27-2: LCDPS: LCD Phase Register330Register 27-3: LCDREF: LCD Reference Voltage Control Register331Register 27-4: LCDCST: LCD Contrast Control Register332Register 27-5: LCDSEn: LCD Segment Enable Registers333Register 27-6: LCDDATAn: LCD Data Registers33327.2 LCD Clock Source Selection33427.2.1 LCD Prescaler334FIGURE 27-2: LCD Clock Generation33427.3 LCD Bias Voltage Generation335TABLE 27-2: LCD Bias Voltages335FIGURE 27-3: LCD Bias VOltage Generation Block DIagram33527.4 LCD Bias Internal Reference Ladder33627.4.1 Bias Mode Interaction336TABLE 27-3: LCD Internal ladder power modes (1/3 Bias)33627.4.2 Power Modes33627.4.3 Automatic power mode switching337FIGURE 27-4: LCD Internal Reference Ladder power mode switching Diagram – Type A337FIGURE 27-5: LCD Internal Reference Ladder power mode switching Diagram – Type A Waveform (1/2 MUX, 1/2 Bias Drive)338FIGURE 27-6: LCD Internal Reference Ladder power mode switching Diagram – Type B Waveform (1/2 MUX, 1/2 Bias Drive)339Register 27-7: LCDRL: LCD Reference Ladder Control Registers34027.4.4 Contrast Control341FIGURE 27-7: Internal reference and Contrast control Block Diagram34127.4.5 Internal Reference34127.4.6 VLCD<3:1> pins34127.5 LCD Multiplex Types342TABLE 27-4: Common Pin Usage34227.6 Segment Enables34227.7 Pixel Control34227.8 LCD Frame Frequency342TABLE 27-5: Frame Frequency Formulas342TABLE 27-6: Approximate Frame Frequency (in Hz) Using Fosc @ 8 MHz, Timer1 @ 32.768 kHz or LFINTOSC342TABLE 27-7: LCD Segment Mapping Worksheet34327.9 LCD Waveform Generation344FIGURE 27-8: Type-A/Type-B Waveforms in Static Drive344FIGURE 27-9: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive345FIGURE 27-10: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive346FIGURE 27-11: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive347FIGURE 27-12: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive348FIGURE 27-13: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive349FIGURE 27-14: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive350FIGURE 27-15: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive351FIGURE 27-16: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive352FIGURE 27-17: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive353FIGURE 27-18: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive35427.10 LCD Interrupts35527.10.1 LCD Interrupt on Module Shutdown35527.10.2 LCD Frame Interrupts355FIGURE 27-19: Waveforms and Interrupt Timing in Quarter-Duty Cycle Drive (Example – Type-B, Non-Static)35627.11 Operation During Sleep357TABLE 27-8: LCD Module Status During Sleep357FIGURE 27-20: Sleep Entry/Exit when SLPEN = 135827.12 Configuring the LCD Module35927.13 Disabling the LCD Module35927.14 LCD Current Consumption35927.14.1 oscillator selection35927.14.2 LCD Bias source35927.14.3 capacitance of the LCD segments359TABLE 27-9: sUMMARY OF Registers Associated with LCD Operation36028.0 In-Circuit Serial Programming™ (ICSP™)36128.1 High-Voltage Programming Entry Mode361FIGURE 28-1: Vpp Limiter Example Circuit36128.2 Low-Voltage Programming Entry Mode36228.3 Common Programming Interfaces362FIGURE 28-2: ICD RJ-11 Style Connector Interface362FIGURE 28-3: PICkit™ Style Connector Interface362FIGURE 28-4: Typical connection for ICSP™ programming36329.0 Instruction Set Summary36529.1 Read-Modify-Write Operations365TABLE 29-1: Opcode Field Descriptions365TABLE 29-2: Abbreviation Descriptions365FIGURE 29-1: General Format for Instructions366TABLE 29-3: PIC16(L)F1934/6/7 Enhanced Instruction Set367TABLE 29-3: PIC16(L)F1938/9 Enhanced Instruction Set (Continued)36829.2 Instruction Descriptions36930.0 Electrical Specifications379Absolute Maximum Ratings(†)379FIGURE 30-1: PIC16F1934/36/37 Voltage Frequency Graph, -40°C £ Ta £ +125°C380FIGURE 30-2: PIC16LF1934/36/37 Voltage Frequency Graph, -40°C £ Ta £ +125°C380FIGURE 30-3: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature38130.1 DC Characteristics: PIC16(L)F1934/6/7-I/E (Industrial, Extended)382FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd38330.2 DC Characteristics: PIC16(L)F1934/6/7-I/E (Industrial, Extended)38430.3 DC Characteristics: PIC16(L)F1934/6/7-I/E (Power-Down)38730.4 DC Characteristics: PIC16(L)F1934/6/7-I/E38930.5 Memory Programming Requirements39130.6 Thermal Considerations39230.7 Timing Parameter Symbology393FIGURE 30-5: Load Conditions39330.8 AC Characteristics: PIC16(L)F1934/6/7-I/E394FIGURE 30-6: Clock Timing394TABLE 30-1: Clock Oscillator Timing Requirements394TABLE 30-2: Oscillator Parameters395TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)395FIGURE 30-7: CLKOUT and I/O Timing396TABLE 30-4: CLKOUT and I/O Timing Parameters397FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing397FIGURE 30-9: Brown-Out Reset Timing and Characteristics398TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters399FIGURE 30-10: Timer0 and Timer1 External Clock Timings399TABLE 30-6: Timer0 and Timer1 External Clock Requirements400FIGURE 30-11: Capture/Compare/PWM Timings (CCP)400TABLE 30-7: Capture/Compare/PWM Requirements (CCP)400TABLE 30-8: PIC16(L)F1934/6/7 A/D Converter (ADC) Characteristics:401TABLE 30-9: PIC16(L)F1934/6/7 A/D Conversion Requirements401FIGURE 30-12: PIC16(L)F1934/6/7 A/D Conversion Timing (Normal Mode)402FIGURE 30-13: PIC16(L)F1934/6/7 A/D Conversion Timing (Sleep Mode)402TABLE 30-10: Comparator Specifications403TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications403FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing403TABLE 30-12: USART Synchronous Transmission Requirements404FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing404TABLE 30-13: USART Synchronous Receive Requirements404FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)405FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)405FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)406FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)406TABLE 30-14: SPI Mode requirements407FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing407TABLE 30-15: I2C™ Bus Start/Stop Bits Requirements408FIGURE 30-21: I2C™ Bus Data Timing408TABLE 30-16: I2C™ Bus Data Requirements409TABLE 30-17: Cap Sense Oscillator Specifications410FIGURE 30-22: Cap Sense Oscillator41031.0 DC and AC Characteristics Graphs and Charts411FIGURE 31-1: PIC16F1934/6/7 Reset Voltage, BOR = 1.9V411FIGURE 31-2: PIC16F1934/6/7 Hysteresis, BOR = 1.9V411FIGURE 31-3: PIC16F1934/6/7 reset Voltage, BOR = 2.5V412FIGURE 31-4: PIC16F1934/6/7 Hysteresis, BOR = 2.5V412FIGURE 31-5: PIC16F1934/6/7 POR release413FIGURE 31-6: PIC16F1934/6/7 Comparator Hysteresis, High-Power Mode413FIGURE 31-7: PIC16F1934/6/7 Comparator Hysteresis, Low-Power Mode414FIGURE 31-8: PIC16F1934/6/7 Comparator Offset, High-Power Mode, Vdd = 5.5V414FIGURE 31-9: PIC16F1934/6/7 Comparator Response Time, High-Power Mode415FIGURE 31-10: Typical Comparator Response Time Over Temperature, High-Power Mode415FIGURE 31-11: Voh vs. Ioh Over Temperature (Vdd = 5.0V)416FIGURE 31-12: Vol vs. Iol Over Temperature (Vdd = 5.0V)416FIGURE 31-13: Voh vs. Ioh Over Temperature (Vdd = 3.0V)416FIGURE 31-14: Vol vs. Iol Over Temperature (Vdd = 3.0V)417FIGURE 31-15: Voh vs. Ioh Over Temperature (Vdd = 1.8V)417FIGURE 31-16: Vol vs. Iol Over Temperature (Vdd = 1.8V)417FIGURE 31-17: PIC16LF1937 HF INTOSC Mode, Fosc = 8 MHz418FIGURE 31-18: PIC16F1937 MF INTOSC Mode, Fosc = 500 kHz418FIGURE 31-19: PIC16LF1937 HF INTOSC Mode, Fosc = 16 MHz418FIGURE 31-20: PIC16F1937 HF INTOSC Mode, Fosc = 16 MHz419FIGURE 31-21: PIC16F1937 HF INTOSC Mode, Fosc = 8 MHz419FIGURE 31-22: PIC16F1937 LF INTOSC Mode, Fosc = 32 kHz419FIGURE 31-23: PIC16LF1937 LF INTOSC Mode, Fosc = 32 kHz420FIGURE 31-24: PIC16LF1937 MF INTOSC Mode, Fosc = 500 kHz420FIGURE 31-25: PIC16LF1937 LP Oscillator Mode, Fosc = 32 kHz420FIGURE 31-26: PIC16F1937 LP Oscillator Mode, Fosc = 32 kHz421FIGURE 31-27: PIC16LF1937 HS Oscillator Mode, Fosc = 32 MHz421FIGURE 31-28: PIC16F1937 HS Oscillator Mode, Fosc = 32 MHz421FIGURE 31-29: PIC16LF1937 EXTRC Mode, Fosc = 4 MHz422FIGURE 31-30: PIC16LF1937 XT Oscillator, Fosc = 1 MHz422FIGURE 31-31: PIC16F1937 XT Oscillator, Fosc = 1 MHz422FIGURE 31-32: PIC16LF1937 XT Oscillator, Fosc = 4 MHz423FIGURE 31-33: PIC16F1937 XT Oscillator, Fosc = 4 MHz423FIGURE 31-34: PIC16LF1937 EC Oscillator, High-Power Mode, Fosc = 32 MHz423FIGURE 31-35: PIC16F1937 EC Oscillator, High-Power Mode, Fosc = 32 MHz424FIGURE 31-36: PIC16LF1937 EC Oscillator, Medium-Power Mode, Fosc = 4 MHz424FIGURE 31-37: PIC16F1937 EC Oscillator, Medium-Power Mode, Fosc = 4 MHz424FIGURE 31-38: PIC16LF1937 EC Oscillator, Low-Power Mode, Fosc = 500 kHz425FIGURE 31-39: PIC16F1937 EC Oscillator, low-Power Mode, Fosc = 500 kHz425FIGURE 31-40: PIC16F1937 EXTRC Mode, Fosc = 4 MHz425FIGURE 31-41: PIC16LF1937 LCD, Low power426FIGURE 31-42: PIC16LF1937 LCD, Medium Power426FIGURE 31-43: PIC16LF1937 LCD, High Power427FIGURE 31-44: PIC16LF1937 A/D Current427FIGURE 31-45: PIC16F1937 A/D Current427FIGURE 31-46: PIC16LF1937 HF INTOSC428FIGURE 31-47: PIC16F1937 HF INTOSC428FIGURE 31-48: PIC16LF1937 Comparator 1, High Power428FIGURE 31-49: PIC16F1937 Comparator 1, High Power429FIGURE 31-50: PIC16LF1937 Comparator 1, Low Power429FIGURE 31-51: PIC16F1937 Comparator 1, Low Power430FIGURE 31-52: PIC16LF1937 Cap Sense, High Power430FIGURE 31-53: PIC16F1937 Cap Sense, High Power431FIGURE 31-54: PIC16LF1937 Cap Sense, Medium Power431FIGURE 31-55: PIC16F1937 Cap Sense, Medium Power431FIGURE 31-56: PIC16LF1937 Comparator 2, High Power432FIGURE 31-57: PIC16F1937 Comparator 2, High Power432FIGURE 31-58: PIC16LF1937 Comparator 2, low Power432FIGURE 31-59: PIC16F1937 Comparator 2, Low Power433FIGURE 31-60: PIC16LF1937 Cap Sense, Low Power433FIGURE 31-61: PIC16F1937 Cap Sense, Low Power433FIGURE 31-62: PIC16LF1937 Timer 1 Oscillator434FIGURE 31-63: PIC16F1937 Timer 1 Oscillator434FIGURE 31-64: PIC16LF1937 BOR Current434FIGURE 31-65: PIC16F1937 BOR Current435FIGURE 31-66: PIC16LF1937 FVR_ADC435FIGURE 31-67: PIC16F1937 FVR_ADC436FIGURE 31-68: PIC16LF1937 WDT436FIGURE 31-69: PIC16F1937 WDT437FIGURE 31-70: PIC16LF1937 FVR_DAC437FIGURE 31-71: PIC16F1937 FVR_DAC437FIGURE 31-72: PIC16LF1937 Base Ipd438FIGURE 31-73: PIC16F1937 Base Ipd43832.0 Development Support43933.0 Packaging Information44333.1 Package Marking Information443Package Marking Information (Continued)444Package Marking Information (Continued)44533.2 Package Details446Appendix A: Data Sheet Revision History459Revision A (12/2008)459Revision B (04/2009)459Revision C (10/2009)459Revision D (12/2009)459Revision E (5/2011)459Appendix B: Migrating From Other PIC® Devices459TABLE B-1: Feature Comparison459INDEX461The Microchip Web Site469Customer Change Notification Service469Customer Support469Reader Response470Product Identification System471Worldwide Sales and Service472Dimensioni: 4,51 MBPagine: 472Language: EnglishApri il manuale