Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Scheda Tecnica
Codici prodotto
TMDSEVM6472LE
PRODUCTPREVIEW
P48
H1
H2
H3
N
1Fh
N+1
N+2
N
N+1
N+2
12
11
9
10
14
8
7
6
5
URCLK
(input)
URDATA[15:0]
(input)
URADDR[4:0]
(input)
URCLA
(output)
V
URENB
(input)
URSOC
(input)
13
15
1Fh
1Fh
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
Table 7-146. Timing Requirements for UTOPIA Slave Receive Cycles
(see
500/625/700
NO.
UNIT
MIN
MAX
5
t
su(URDATA
−
URCLKH)
Setup time, URDATA valid before URCLK high
4
ns
6
t
h(URCLKH
−
URDATA)
Hold time, URDATA valid after URCLK high
1
ns
7
t
su(URADDR
−
URCLKH)
Setup time, URADDR valid before URCLK high
4
ns
8
t
h(URCLKH
−
URADDR)
Hold time, URADDR valid after URCLK high
1
ns
9
t
su(URENB
−
URCLKH)
Setup time, URENB valid before URCLK high
4
ns
10
t
h(URCLKH
−
URENB)
Hold time, URENB valid after URCLK high
1
ns
11
t
su(URSOC
−
URCLKH)
Setup time, URSOC valid before URCLK high
4
ns
12
t
h(URCLKH
−
URSOC)
Hold time, URSOC valid after URCLK high
1
ns
Table 7-147. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Receive Cycles
(see
500/625/700
NO.
PARAMETER
UNIT
MIN
MAX
13
(1)
t
d(URCLKH
−
URCLAV)
Delay time, URCLK high to URCLAV valid
2
10
ns
14
(1)
t
en(URCLKH
−
URCLAV)
Enable time, URCLK high to URCLAV driven
2
10
ns
15
(2) (3)
t
dis(URCLKL
−
URCLAVZ)
Disable time, URCLK low to URCLAV high-impedance state
2
10
ns
(1)
MAX delay time and enable time increases to 12.5 ns at 20 pF and 14 ns at 30 pF, specified by design.
(2)
Specifed by design for MIN values.
(3)
Specifed by design for MAX values.
Figure 7-63. UTOPIA Slave Receive
246
C64x+ Peripheral Information and Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
Product Folder Link(s) :