Texas Instruments DS100KR800EVK evaluation board DS100KR800EVK/NOPB DS100KR800EVK/NOPB Scheda Tecnica
Codici prodotto
DS100KR800EVK/NOPB
OUT_B_0+
OUT_B_0-
OUT_B_1+
R
ESER
VED
IN
PU
T
_
EN
AL
L_
D
O
N
E
1
2
3
4
2
6
2
5
DAP = GND
OUT_B_1-
OUT_B_2+
OUT_B_2-
5
6
7
2
4
2
1
2
0
2
3
IN_A_3-
8
IN_A_0+
IN_A_0-
VDD
IN_A_1+
9
10
11
12
IN_A_1-
EQ
A0
IN_A_2+
IN_A_2-
13
18
14
15
IN_A_3+
16
17
OUT_A_1+
OUT_A_1-
EQ
A1
OUT_A_2+
36
34
35
OUT_A_2-
OUT_A_3+
OUT_A_3-
33
31
32
VI
N
VD
D
_
SEL
IN_B_3+
IN_B_3-
VDD
41
40
39
MO
D
E
OUT_A_0+
OUT_A_0-
37
38
IN_B_0+
IN_B_0-
IN_B_1+
IN_B_1-
IN_B_2-
IN_B_2+
44
42
43
VD
D
D
EMA
1
/SC
L
5
0
4
8
4
7
4
9
D
EMA
0
/SD
A
EN
SMB
4
6
5
1
OUT_B_3+
OUT_B_3-
SMBUS AND CONTROL
D
EMB
1
/AD
0
D
EMB
0
/AD
1
30
29
28
SD
_
T
H
A/
R
EAD_
EN
5
2
EQ
B
1
/AD
2
EQ
B
0
/AD
3
1
9
2
2
R
ESET
2
7
45
5
3
5
4
VDD
VDD
Vreg
SNLS340D – NOVEMBER 2011 – REVISED APRIL 2013
Pin Diagram
Figure 1. DS100KR800 Pin Diagram 54 lead
Pin Descriptions
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
IN_B_0+, IN_B_0-,
1, 2,
I
Inverting and non-inverting differential inputs to bank B equalizer. A
IN_B_1+, IN_B_1-,
3, 4,
gated on-chip 50
Ω
termination resistor connects INB_n+ to VDD and
IN_B_2+, IN_B_2-,
5, 6,
INB_n- to VDD when enabled.
IN_B_3+, IN_B_3-,
7, 8
IN_A_0+, IN_A_0-,
10, 11,
I
Inverting and non-inverting differential inputs to bank A equalizer. A
IN_A_1+, IN_A_1-,
12, 13,
gated on-chip 50
Ω
termination resistor connects INA_n+ to VDD and
IN_A_2+, IN_A_2-,
15, 16,
INA_n- to VDD when enabled.
IN_A_3+, IN_A_3-
17, 18
Copyright © 2011–2013, Texas Instruments Incorporated
3
Product Folder Links: