Microchip Technology DM300023 Scheda Tecnica
dsPIC30F1010/202X
DS70178C-page 192
Preliminary
©
2006 Microchip Technology Inc.
17.3
Module Description
The Comparator module uses a 20 nsec comparator.
The comparator offset is ±5 mV typical. The negative
input of the comparator is always connected to the
DAC circuit. The positive input of the comparator is
connected to an analog multiplexer that selects the
desired source pin.
The comparator offset is ±5 mV typical. The negative
input of the comparator is always connected to the
DAC circuit. The positive input of the comparator is
connected to an analog multiplexer that selects the
desired source pin.
17.4
DAC
The range of the DAC is controlled via an analog mul-
tiplexer that selects either AV
tiplexer that selects either AV
DD
/2, internal 1.2V 1%
reference, or an external reference source EXTREF.
The full range of the DAC (AV
The full range of the DAC (AV
DD
/2) will typically be
used when the chosen input source pin is shared with
the ADC. The reduced range option (INTREF) will
likely be used when monitoring current levels via a
CLx pin using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V), therefore the option of using a reduced ref-
erence range for the comparator extends the available
DAC resolution in these applications. The use of an
external reference enables the user to connect to a
reference that better suits their application.
the ADC. The reduced range option (INTREF) will
likely be used when monitoring current levels via a
CLx pin using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V), therefore the option of using a reduced ref-
erence range for the comparator extends the available
DAC resolution in these applications. The use of an
external reference enables the user to connect to a
reference that better suits their application.
17.5
Interaction with I/O Buffers
If the comparator module is enabled and a pin has
been selected as the source for the comparator, then
the chosen I/O pad must disable the digital input buffer
associated with the pad to prevent excessive currents
in the digital buffer due to analog input voltages.
been selected as the source for the comparator, then
the chosen I/O pad must disable the digital input buffer
associated with the pad to prevent excessive currents
in the digital buffer due to analog input voltages.
17.6
Digital Logic
The CMPCONx register (see Register 17-1) provides
the control logic that configures the Comparator mod-
ule. The digital logic provides a glitch filter for the com-
parator output to mask transient signals less than two
T
the control logic that configures the Comparator mod-
ule. The digital logic provides a glitch filter for the com-
parator output to mask transient signals less than two
T
CY
(66 nsec) in duration. In Sleep or Idle mode, the
glitch filter is bypassed to enable an asynchronous
path from the comparator to the interrupt controller.
This asynchronous path can be used to wake-up the
processor from Sleep or Idle mode.
path from the comparator to the interrupt controller.
This asynchronous path can be used to wake-up the
processor from Sleep or Idle mode.
The comparator can be disabled while in Idle mode if
the CMPSIDL bit is set. If a device has multiple com-
parators, if any CMPSIDL bit is set, then the entire
group of comparators will be disabled while in Idle
mode. This behavior reduces complexity in the design
of the clock control logic for this module.
the CMPSIDL bit is set. If a device has multiple com-
parators, if any CMPSIDL bit is set, then the entire
group of comparators will be disabled while in Idle
mode. This behavior reduces complexity in the design
of the clock control logic for this module.
The digital logic also provides a one T
CY
width pulse
generator for triggering the ADC and generating
interrupt requests.
interrupt requests.
The CMPDACx (see Register 17-2) register provides
the digital input value to the reference DAC.
the digital input value to the reference DAC.
If the module is disabled, the DAC and comparator are
disabled to reduce power consumption.
disabled to reduce power consumption.
17.7
Comparator Input Range
The comparator has a limitation for the input Common
Mode Range (CMR) of about 3.5 volts (AV
Mode Range (CMR) of about 3.5 volts (AV
DD
– 1.5
volts). This means that both inputs should not exceed
this value, or the comparator’s output will become
indeterminate. As long as one of the inputs is within
the Common Mode Range, the comparator output will
be correct. An input excursion into the CMR region will
not corrupt the comparator output, but the comparator
input is saturated.
this value, or the comparator’s output will become
indeterminate. As long as one of the inputs is within
the Common Mode Range, the comparator output will
be correct. An input excursion into the CMR region will
not corrupt the comparator output, but the comparator
input is saturated.
17.8
DAC Output Range
The DAC has a limitation for the maximum reference
voltage input of (AV
voltage input of (AV
DD
- 1.6) volts. An external refer-
ence voltage input should not exceed this value or the
reference DAC output will become indeterminate.
reference DAC output will become indeterminate.
17.9
Comparator Registers
The Comparator module is controlled by the following
registers:
registers: