Scheda TecnicaSommarioTABLE 1: Silicon DEVREV Values1TABLE 2: Silicon Issue Summary2Silicon Errata Issues51. Module: PWM52. Module: PWM53. Module: PWM54. Module: PWM55. Module: PWM66. Module: PWM6EQUATION 1:67. Module: PWM7TABLE 1:7EQUATION 2:7EQUATION 3:78. Module: ADC79. Module: ADC810. Module: ADC811. Module: ADC812. Module: PWM813. Module: Output Compare914. Module: PWM915. Module: Output Compare916. Module: SPI917. Module: SPI1018. Module: SPI1019. Module: UART1020. Module: UART1021. Module: UART1022. Module: UART1123. Module: UART1124. Module: UART1125. Module: UART11TABLE 2:1126. Module: UART1127. Module: I2C™1228. Module: I2C1229. Module: I2C1230. Module: I2C1231. Module: MCLR12FIGURE 1:13EXAMPLE 1: Clock Switching Example1332. Module: CPU14EXAMPLE 2: Check Carry Bit Before DAW.b1433. Module: PWM1434. Module: PWM1435. Module: UART1436. Module: UART1437. Module: SPI1538. Module: I2C1539. Module: I2C1540. Module: I2C1541. Module: I2C1542. Module: UART1643. Module: PSV1644. Module: FRC16Data Sheet Clarifications17Appendix A: Revision History18Worldwide Sales and Service20Dimensioni: 362 KBPagine: 20Language: EnglishApri il manuale
Scheda TecnicaSommarioSilicon Errata Summary11. Module: Power Supply PWM: Dead Time42. Module: Power Supply PWM: Duty Cycle43. Module: Power Supply PWM: Special Event Trigger and Individual Trigger44. Module: PWM Override Enable45. Module: PWM Duty Cycle56. Module: PWM Override Priority5EQUATION 1:57. Module: PWM Jitter6TABLE 1:6EQUATION 2:6EQUATION 3:68. Module: ADC Module: Global Software Trigger69. Module: ADC Sample and Hold Timing710. Module: ADC Interrupts711. Module: ADC Module: Conversion Rate712. Module: Current Reset Mode713. Module: Output Compare Module714. Module: Output Compare Module in PWM Mode815. Module: Output Compare Module816. Module: SPI Module in Slave Select Mode817. Module: SPI Module in Frame Master Mode818. Module: SPI Module919. Module: UART Module920. Module: UART Module921. Module: UART Module922. Module: UART Module923. Module: UART Module924. Module: UART Module925. Module: UART Module10TABLE 2:1026. Module: UART Module1027. Module: I2C Module1028. Module: I2C Module1029. Module: I2C Module1030. Module: I2C Module1031. Module: MCLR Pin11FIGURE 1:11EXAMPLE 1: Clock Switching Example1132. Module: CPU – DAW.b instruction12EXAMPLE 2: Check Carry Bit Before DAW.b1233. Module: PWM Module1234. Module: Power Supply PWM1235. Module: UART Module1236. Module: UART Module1237. Module: SPI Module1238. Module: I2C Module1239. Module: I2C Module1240. Module: I2C Module1341. Module: I2C Module1342. Module: UART (FIFO Error Flags)1343. Module: PSV Operations13Appendix A: Revision History14Dimensioni: 198 KBPagine: 16Language: EnglishApri il manuale
Scheda TecnicaSommarioSilicon Errata Summary11. Module: Power Supply PWM: Dead Time42. Module: Power Supply PWM: Duty Cycle43. Module: Power Supply PWM: Special Event Trigger and Individual Trigger44. Module: PWM Override Enable45. Module: PWM Duty Cycle56. Module: PWM Override Priority5EQUATION 1:57. Module: PWM Jitter6TABLE 1:6EQUATION 2:6EQUATION 3:68. Module: ADC Module: Global Software Trigger69. Module: ADC Sample and Hold Timing710. Module: ADC Interrupts711. Module: ADC Module: Conversion Rate712. Module: ADC Module: Shared Sample and Hold Circuit713. Module: Current Reset Mode714. Module: Output Compare Module715. Module: Output Compare Module in PWM Mode816. Module: Output Compare Module817. Module: SPI Module in Slave Select Mode818. Module: SPI Module in Frame Master Mode819. Module: SPI Module920. Module: UART Module921. Module: UART Module922. Module: UART Module923. Module: UART Module924. Module: UART Module925. Module: UART Module926. Module: UART Module10TABLE 2:1027. Module: UART Module1028. Module: I2C Module1029. Module: I2C Module1030. Module: I2C Module1031. Module: I2C Module1032. Module: MCLR Pin11FIGURE 1:11EXAMPLE 1: Clock Switching Example1133. Module: CPU – DAW.b instruction12EXAMPLE 2: Check Carry Bit Before DAW.b1234. Module: Sleep Mode12EXAMPLE 3:1335. Module: PWM Module1436. Module: PWM Module1437. Module: Power Supply PWM1438. Module: UART Module1439. Module: UART Module1440. Module: SPI Module1441. Module: I2C Module1442. Module: I2C Module1443. Module: I2C Module1544. Module: I2C Module1545. Module: UART (FIFO Error Flags)1546. Module: Module: PSV Operations15Appendix A: Revision History16Dimensioni: 222 KBPagine: 18Language: EnglishApri il manuale
Scheda TecnicaSommario1. Module: Power Supply PWM: Dead Time42. Module: Power Supply PWM: Duty Cycle43. Module: Power Supply PWM: Special Event Trigger and Individual Trigger44. Module: ADC Sample and Hold Timing45. Module: ADC Interrupts56. Module: ADC Module: Shared Sample and Hold Circuit57. Module: ADC Module: Global Software Trigger58. Module: RB7 Pin and All Multiplexed Functions69. Module: ADC Module: Conversion Rate610. Module: Current Reset Mode611. Module: PWM Override Enable712. Module: EXTREF Pin813. Module: Output Compare Module914. Module: Output Compare Module in PWM Mode915. Module: SPI Module in Frame Master Mode916. Module: SPI Module in Slave Select Mode917. Module: SPI Module1018. Module: I2C Module1019. Module: MCLR Pin1120. Module: UART Module1221. Module: UART Module1222. Module: UART Module1223. Module: UART Module1224. Module: UART Module1225. Module: UART Module1226. Module: I2C Module1327. Module: I2C Module1328. Module: I2C Module1329. Module: UART Module1330. Module: UART Module1331. Module: Output Compare Module1432. Module: PWM Duty Cycle1433. Module: PWM Jitter1434. Module: PWM Override Priority1535. Module: CPU – DAW.b instruction1536. Module: Sleep Mode1637. Module: PWM Module1738. Module: PWM Module1739. Module: Power Supply PWM1740. Module: UART Module1741. Module: UART Module1742. Module: SPI Module1743. Module: I2C Module1744. Module: I2C Module1845. Module: I2C Module1846. Module: I2C Module1847. Module: UART (FIFO Error Flags)1848. Module: Module: PSV Operations18Dimensioni: 243 KBPagine: 22Language: EnglishApri il manuale
Scheda TecnicaSommarioPreface5Chapter 1. Introduction111.1 Overview11Figure 1-1: synchronous buck converter Block Diagram111.2 dsPICDEM™ SMPS Buck Development Board Kit121.3 dsPICDEM™ SMPS Buck Development Board Features121.3.1 Power Stages121.3.2 Input/Output Controls121.3.3 Development Board Power131.3.4 Communication Ports13Chapter 2. Hardware Overview152.1 Connectors15Figure 2-1: dsPICDEM™ SMPS Buck Development Board connected to MPLAB® ICD 2 and power supply15Table 2-1: Buck Converter Board Connectors152.1.1 Input Power Connector162.1.2 ICD Connector162.1.3 RS-232 Serial Port162.1.4 VOUT1162.1.5 VOUT2162.1.6 Expansion Header16Table 2-2: Device Pins in Expansion connector172.2 User Interface Hardware18Figure 2-2: Jumpers/LED/Switches/Potentiometer182.2.1 Jumpers18Table 2-3: Jumper Descriptions182.2.2 Switches, LEDs and Potentiometers19Table 2-4: Push buttons, Potentiometers and LEDs192.2.3 Test Points19Figure 2-3: Test Points20Table 2-5: Power Test points20Table 2-6: PWM Test points202.3 Program or Debug Selection Switch (SW2)21Chapter 3. Using the dsPIC30F2020 Device233.1 Tutorial Overview233.2 Creating the Project233.2.1 Select a dsPIC DSC Device24Figure 3-1: PROJECT WIZARD, STEP 1, SELECT A DEVICE24Figure 3-2: Project wizard STEP 2, SELECT LANGUAGE TOOLSUITE253.2.2 Select Language Toolsuite25Figure 3-3: PROJECT WIZARD, STEP 3, NAME YOUR PROJECT263.2.3 Name Your Project26Figure 3-4: PROJECT WIZARD, STEP 4, ADD FILES TO PROJECT273.2.4 Add Files to Project27Figure 3-5: Save Workspace Window28Figure 3-6: MPLAB® IDE PROJECT WINDOw28Figure 3-7: MPLAB® IDE WORKSPACE WINDOWS293.3 Building the Code30Figure 3-8: BUILD OPTIONS303.3.1 Identify Assembler Include Path313.3.2 Link for ICD 231Figure 3-9: Link Project for MPLAB® ICD 2313.3.3 Build the Project32Figure 3-10: BUILD OUTPUT WINDOW323.4 Programming the Chip323.4.1 Setup the Device Configuration32Figure 3-11: CONFIGURATION SETTINGS323.4.2 Connect the MPLAB ICD 2 In-Circuit Debugger33Figure 3-12: dsPICDEM™ SMPS Buck DEVELOPMENT BOARD CONNECTED TO MPLAB® ICD 2 IN-CIRCUIT DEBUGGER333.4.3 Enable MPLAB ICD 2 Connection34Figure 3-13: ENABLING MPLAB® ICD 234Figure 3-14: SETTING PROGRAM MEMORY SIZE353.4.4 Program the dsPIC30F202035Figure 3-15: PROGRAMMING THE dsPIC30F2020 DEVICE363.5 Debugging the Code373.5.1 Display the Code37Figure 3-16: PROGRAM MEMORY WINDOW373.5.2 Step the Program38Figure 3-17: Source Code Window38Figure 3-18: Watch Window Display383.5.3 Set Break Point39Figure 3-19: Setting Breakpoint39Chapter 4. Demonstration Program Operation414.1 Demonstration Program41Figure 4-1: SMPS Demonstration Program Flow Chart424.2 Demonstration Code434.2.1 System Initialization434.2.2 Fault Check434.2.3 Soft Start434.2.4 ADC Interrupt434.2.5 System Idle Loop434.3 Other Code Examples44Figure A-1: dsPICDEM™ SMPS Buck Development Board Layout45Figure A-2: dsPICDEM™ SMPS Buck Development Board Schematic 1 of 346Figure A-3: dsPICDEM™ SMPS Buck Development Board Schematic 2 of 347Figure A-4: dsPICDEM™ SMPS Buck Development Board Schematic 3 of 348Index49Worldwide Sales and Service50Dimensioni: 6,88 MBPagine: 50Language: EnglishApri il manuale
Scheda TecnicaSommario28/44-Pin dsPIC30F1010/202X Enhanced Flash SMPS 16-Bit Digital Signal Controller31.0 Device Overview11FIGURE 1-1: dsPIC30F1010 Block Diagram12TABLE 1-1: PINOUT I/O DeSCRIPTIONS for dsPIC30F101013FIGURE 1-2: dspic30f2020 block diagram15TABLE 1-2: PINOUT I/O DeSCRIPTIONS for dsPIC30F202016FIGURE 1-3: dsPIC30F2023 Block Diagram18TABLE 1-3: PINOUT I/O DeSCRIPTIONS for dsPIC30F2023192.0 CPU Architecture Overview212.1 Core Overview212.2 Programmer’s Model222.2.1 Software Stack Pointer/ FRAMe pointer222.2.2 Status Register222.2.3 program counter22FIGURE 2-1: Programmer’s Model232.3 Divide Support24TABLE 2-1: Divide Instructions242.4 DSP Engine25TABLE 2-2: DSP Instruction Summary25FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM262.4.1 Multiplier272.4.2 Data Accumulators and Adder/Subtracter272.4.2.1 Adder/Subtracter, Overflow and Saturation272.4.2.2 Accumulator ‘Write Back’282.4.2.3 Round Logic282.4.2.4 Data Space Write Saturation292.4.3 Barrel Shifter293.0 Memory Organization313.1 Program Address Space31FIGURE 3-1: program Space memory map FOR dsPIC30F1010/ 202X31TABLE 3-1: Program Space Address Construction32FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION323.1.1 Data Access From Program Memory using Table Instructions33FIGURE 3-3: Program Data Table Access (Least Significant Word)33FIGURE 3-4: Program Data Table Access (Most Significant Byte)343.1.2 Data Access from Program Memory Using Program Space Visibility34FIGURE 3-5: Data Space Window Into Program Space Operation353.2 Data Address Space353.2.1 Data Space Memory Map35FIGURE 3-6: DATA SPACE MEMORY MAP36FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS373.2.2 Data Spaces38TABLE 3-2: Effect of Invalid Memory Accesses383.2.3 Data Space Width383.2.4 Data Alignment38FIGURE 3-8: DATA ALIGNMENT383.2.5 Near Data Space393.2.6 Software Stack39FIGURE 3-9: CALL Stack FRAME393.2.7 Data RAM Protection39TABLE 3-3: Core Register Map404.0 Address Generator Units434.1 Instruction Addressing Modes434.1.1 file register instructions43TABLE 4-1: Fundamental Addressing Modes Supported434.1.2 mcu instructions444.1.3 Move and accumulator instructions444.1.4 Mac instructions444.1.5 other instructions444.2 Modulo Addressing454.2.1 Start and End Address454.2.2 W Address Register Selection45FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE464.2.3 Modulo Addressing Applicability474.3 Bit-Reversed Addressing474.3.1 Bit-Reversed Addressing Implementation47FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE47TABLE 4-2: BiT-Reversed Address Sequence (16-entry)48TABLE 4-3: Bit-Reversed Address Modifier Values For XBREV Register485.0 Interrupts495.1 Interrupt Priority50TABLE 5-1: dsPIC30F1010/202X Interrupt Vector Table505.2 Reset Sequence515.2.1 Reset Sources515.3 Traps515.3.1 Trap Sources515.3.2 Hard and Soft Traps52FIGURE 5-1: Trap VECTORS525.4 Interrupt Sequence53FIGURE 5-2: INTERRUPT STACK FRAME535.5 Alternate Vector Table535.6 Fast Context Saving535.7 External Interrupt Requests535.8 Wake-up from Sleep and Idle53Register 5-1: IntCON1: Interrupt Control Register 154Register 5-2: INTCON2: Interrupt Control REgister 256Register 5-3: IFs0: Interrupt Flag Status Register 057Register 5-4: IFS1: Interrupt Flag STatus Register 159Register 5-5: IFS2: Interrupt Flag Status Register 260Register 5-6: IEC0: Interrupt Enable Control Register 061Register 5-7: IEC1: Interrupt Enable Control Register 163Register 5-8: IEC2: Interrupt Enable Control Register 264Register 5-9: IPC0: Interrupt Priority Control Register 065Register 5-10: IPC1: Interrupt Priority Control Register 166Register 5-11: IPC2: Interrupt Priority Control Register 267Register 5-12: IPC3: Interrupt Priority Control Register 368Register 5-13: IPC4: Interrupt Priority Control Register 469Register 5-14: IPC5: Interrupt Priority Control Register 570Register 5-15: IPC6: Interrupt Priority Control Register 671Register 5-16: IPC7: Interrupt Priority Control Register 772Register 5-17: IPC8: INterrupt Priority Control Register 873Register 5-18: IPC9: INterrupt Priority Control Register 974Register 5-19: IPC10: INterrupt Priority Control Register 1075Register 5-20: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER76TABLE 5-2: Interrupt Controller Register Map776.0 I/O Ports796.1 Parallel I/O (PIO) Ports79FIGURE 6-1: Block Diagram of a ShAred PORT Structure796.2 Configuring Analog Port Pins806.2.1 I/O Port Write/Read Timing80EXAMPLE 6-1: Port Write/Read Example806.3 Input Change Notification80TABLE 6-1: dsPIC30F1010/2020 Port Register MAp81TABLE 6-2: dsPIC30F2023 Port Register MAp82TABLE 6-3: dsPIC30F1010/202x INPUT CHANGE NOTIFICATION REGISTER MAP827.0 Flash Program Memory837.1 In-Circuit Serial Programming (ICSP)837.2 Run-Time Self-Programming (RTSP)837.3 Table Instruction Operation Summary83FIGURE 7-1: ADDRESSING FOR TABLE AND NVM REGISTERS837.4 RTSP Operation847.5 Control Registers847.5.1 NVMCON Register847.5.2 NVMADR Register847.5.3 NVMADRU Register847.5.4 NVMKEY Register847.6 Programming Operations857.6.1 Programming Algorithm for Program Flash857.6.2 Erasing a Row of Program Memory85EXAMPLE 7-1: erasing A row of PROGRAM memory857.6.3 Loading Write Latches86EXAMPLE 7-2: loading write latches867.6.4 Initiating The Programming Sequence86EXAMPLE 7-3: initiating a programming sequence86TABLE 7-1: NVM Register Map878.0 Timer1 Module89FIGURE 8-1: 16-bit Timer1 Module Block diagram (Type A Timer)908.1 Timer Gate Operation908.2 Timer Prescaler908.3 Timer Operation During Sleep Mode908.4 Timer Interrupt91TABLE 8-1: Timer1 Register Map929.0 Timer2/3 Module93FIGURE 9-1: 32-bit TIMER2/3 BLOCK DIAGRAM94FIGURE 9-2: 16-bit TIMER2 BLOCK DIAGRAM95FIGURE 9-3: 16-bit TIMER3 BLOCK DIAGRAM959.1 Timer Gate Operation969.2 ADC Event Trigger969.3 Timer Prescaler969.4 Timer Operation During Sleep Mode969.5 Timer Interrupt96TABLE 9-1: Timer2/3 register map9710.0 Input Capture Module99FIGURE 10-1: Input Capture Mode Block Diagram9910.1 Simple Capture Event Mode10010.1.1 Capture Prescaler10010.1.2 Capture Buffer Operation10010.1.3 Timer2 and Timer3 selection mode10010.1.4 Hall Sensor Mode10010.2 Input Capture Operation During Sleep and Idle Modes10110.2.1 Input Capture in CPU Sleep Mode10110.2.2 Input Capture in CPU Idle Mode10110.3 Input Capture Interrupts101TABLE 10-1: Input Capture Register Map10211.0 Output Compare Module103FIGURE 11-1: Output Compare Mode Block DiagrAm10311.1 Timer2 and Timer3 Selection Mode10411.2 Simple Output Compare Match Mode10411.3 Dual Output Compare Match Mode10411.3.1 Single Pulse Mode10411.3.2 Continuous Pulse Mode10411.4 Simple PWM Mode10411.4.1 PWM Period105EQUATION 11-1: PWM Period10511.4.2 PWM with FAULt protection Input pin10511.5 Output Compare Operation During CPU Sleep Mode10511.6 Output Compare Operation During CPU Idle Mode105FIGURE 11-1: PWM output Timing10611.7 Output Compare Interrupts106TABLE 11-1: Output Compare Register Map10712.0 Power Supply PWM10912.1 Features Overview10912.2 Description109FIGURE 12-1: Simplified Conceptual Block Diagram of Power Supply PWM110FIGURE 12-2: Partitioned output Pair, complementary PWM Mode11112.3 Control Registers111Register 12-1: PTCON: PWM Time Base Control Register112Register 12-2: PTPER: Primary Time Base Register113Register 12-3: SEVTCMP: PWM Special Event Compare Register113Register 12-4: MDC: PWM Master Duty Cycle Register114Register 12-5: PWMCONx: PWM Control Register114Register 12-6: PDCx: PWM Generator Duty Cycle Register115Register 12-7: PHASEx: PWM Phase-Shift Register116Register 12-8: DTRx: PWM Dead-Time Register116Register 12-9: ALTDTRx: PWM Alternate Dead-Time Register117Register 12-10: TRGCONx: PWM TRIGGER Control Register117Register 12-11: IOCONx: PWM I/O Control Register118Register 12-12: FCLCONx: PWM Fault Current-Limit Control Register119Register 12-13: TRIGx: PWM Trigger Compare Value Register121Register 12-14: LEBCONx: Leading Edge Blanking Control Register12212.4 Module Functionality12312.4.1 Standard Edge-Aligned PWM Mode123FIGURE 12-3: Edge-Aligned PWM12312.4.2 Complementary PWM Mode123FIGURE 12-4: Complementary PWM12312.4.3 Push-Pull PWM Mode123FIGURE 12-5: Push-Pull PWM12312.4.4 Multi-Phase PWM Mode124FIGURE 12-6: Multi-Phase PWM12412.4.5 Variable Phase PWM Mode124FIGURE 12-7: Variable Phase PWM12412.4.6 Current-Limit PWM Mode124FIGURE 12-8: Cycle-by-Cycle Current-LIMIT PWM Mode12412.4.7 Constant Off-Time PWM125FIGURE 12-9: Constant Off-Time PWM12512.4.8 Current Reset PWM Mode125FIGURE 12-10: Current Reset PWM12512.4.9 Independent Time Base PWM125FIGURE 12-11: Independent Time base PWM12512.5 Primary PWM Time Base126FIGURE 12-12: PTMR Block Diagram12612.5.1 PTMR Synchronization12612.6 Primary PWM Time Base Roll Counter12612.7 Individual PWM Time Base(s)126FIGURE 12-13: TMRx Block Diagram12712.8 PWM Period12712.9 PWM Frequency and Duty Cycle Resolution127TABLE 12-1: Available Pwm frequencies and resolutions @ 30 MIPS127TABLE 12-2: Available Pwm frequencies and resolutions @ 20 MIPS12712.10 PWM Duty Cycle Comparison Units128FIGURE 12-14: Duty Cycle Comparison12812.11 Complementary PWM Outputs12812.12 Independent PWM Outputs12812.13 Duty Cycle Limits12812.14 Dead-Time Generation129FIGURE 12-15: Dead-Time Insertion for Complementary PWM129FIGURE 12-16: Dead-time Control Units block diagram12912.14.1 DEAD-TIME GENERATORS12912.14.2 Alternate Dead-Time Source129FIGURE 12-17: DUal dead-time waveforms13012.14.3 Dead-Time ranges130TABLE 12-3: Example Dead-Time Ranges13012.14.4 Dead-Time Insertion Timing13012.14.5 Dead-Time distortion130FIGURE 12-18: Dead-Time insertion (PWM OUTPUT SIGNAL TIMING MAY BE DELAYED)13012.15 Configuring a PWM Channel13112.16 Speed Limits of PWM Output Circuitry13112.17 PWM Special Event Trigger13112.17.1 Special Event Trigger Enable13112.17.2 Special Event Trigger postscaler13112.18 Individual PWM Triggers131EXAMPLE 12-1: Code Example for Configuring PWM Channel 1132FIGURE 12-19: PWM Trigger Block Diagram13312.19 PWM Interrupts13312.20 PWM Time Base Interrupts13312.21 PWM Fault and Current-Limit Pins13312.22 Leading Edge Blanking13312.23 PWM Fault Pins134FIGURE 12-20: PWM Fault Control Logic Diagram13412.23.1 Fault Interrupts13512.23.2 Fault states13512.23.3 Fault input modes13512.23.4 Fault ENTRY13512.23.5 Fault EXIT13512.23.6 Fault exit with PTMR disabled13512.23.7 Fault Pin Software Control13512.24 PWM Current-Limit Pins13612.24.1 Current-Limit Interrupts136FIGURE 12-21: PWM Current-Limit Control Logic Diagram13612.25 Simultaneous PWM Faults and Current Limits13712.26 PWM Fault and Current-Limit TRG Outputs To ADC13712.27 PWM Output Override Priority13712.28 Fault and Current-Limit Override Issues with Dead-Time Logic13712.29 Asserting Outputs via Current Limit13712.30 PWM Immediate Update13712.31 PWM Output Override13712.31.1 complementary output mode13712.31.2 override synchronization13812.32 Functional Exceptions13812.32.1 Power Reset Conditions13812.32.2 SLEEP Mode13812.32.3 CPU IDLE Mode13812.33 Register Bit Alignment13812.34 Application Examples:13912.34.1 Standard PWM Mode139FIGURE 12-22: Applications of Standard PWM Mode13912.34.2 Application of Complementary PWM Mode139FIGURE 12-23: Applications of Complementary PWM mode13912.34.3 Application of Push-Pull PWM Mode140FIGURE 12-24: Applications of Push- Pull Pwm Mode14012.34.4 Application of Multi-Phase PWM Mode140FIGURE 12-25: Applications of Multi- Phase Pwm Mode14012.34.5 Application of Variable Phase PWM Mode141FIGURE 12-26: Application of Variable Phase PWM mode14112.34.6 Application of Current Reset PWM Mode141FIGURE 12-27: Application of Current Reset PWM mode14112.35 Methods to reduce EMI14212.35.1 Method #1: programmable FRC dither14212.35.2 Method #2: Software Controlled Dither14212.35.3 Method #3: Software Scaling of Time Base Period14212.35.4 Method #4: Frequency Modulation14212.35.5 INDEPENDENT PWM CHANNEL DITHERING ISSUES:14212.36 External Synchronization Features14312.37 CPU Load Staggering14312.38 External Trigger Blanking143TABLE 12-4: Power Supply PWM Register Map14413.0 Serial Peripheral Interface (SPI)147FIGURE 13-1: SPI Module Block Diagram148FIGURE 13-2: SPI Master/Slave Connection149FIGURE 13-3: SPI Master, Frame Master Connection Diagram149FIGURE 13-4: SPI Master, Frame Slave Connection Diagram149FIGURE 13-5: SPI Slave, Frame Master Connection Diagram150FIGURE 13-6: SPI Slave, Frame Slave Connection Diagram150EQUATION 13-1: Relationship Between Device and SPI Clock Speed150TABLE 13-1: Sample SCKx Frequencies150Register 13-1: SPIxSTAT: SPIx Status and Control Register151Register 13-2: SPIxCON1: SPIx Control Register 1152Register 13-3: SPIxCON2: SPIx Control Register 2153TABLE 13-2: SPI1 Register Map15414.0 I2C™ Module15514.1 Operating Function Description15514.1.1 VARIOUS I2C MODES15514.1.2 Pin Configuration In I2C Mode155FIGURE 14-1: Programmer’s model15514.1.3 I2C Registers155FIGURE 14-2: I2C™ BLOCK DIAGRAM15614.2 I2C Module Addresses15714.3 I2C 7-bit Slave Mode Operation15714.3.1 Slave Transmission15714.3.2 Slave Reception15714.4 I2C 10-bit Slave Mode Operation15714.4.1 10-bit Mode Slave Transmission15714.4.2 10-bit Mode Slave Reception15714.5 Automatic Clock Stretch15814.5.1 transmit Clock Stretching15814.5.2 RECEIVE CLOCK STRETCHING15814.5.3 Clock Stretching During 7-bit Addressing (STREN = 1)15814.5.4 Clock Stretching During 10-bit Addressing (STREN = 1)15814.6 Software Controlled Clock Stretching (STREN = 1)15814.7 Interrupts15814.8 Slope Control15914.9 IPMI Support15914.10 General Call Address Support15914.11 I2C Master Support15914.12 I2C Master Operation15914.12.1 I2C Master Transmission15914.12.2 I2C Master Reception15914.12.3 Baud Rate Generator16014.12.4 Clock Arbitration16014.12.5 Multi-Master Communication, Bus Collision And Bus Arbitration16014.13 I2C Module Operation During CPU Sleep and Idle Modes16014.13.1 I2C Operation During CPU Sleep MoDE16014.13.2 I2C Operation During CPU Idle Mode160TABLE 14-1: I2C™ Register Map16115.0 Universal Asynchronous Receiver Transmitter (UART) Module163FIGURE 15-1: UART Simplified Block Diagram16315.1 UART Baud Rate Generator (BRG)164EQUATION 15-1: UART Baud Rate with BRGH = 0(1,2,3)164EQUATION 15-2: UART Baud Rate with BRGH = 1(1,2,3)164EXAMPLE 15-1: Baud Rate Error Calculation (BRGH = 0)(1)16415.2 Transmitting in 8-bit Data Mode16515.3 Transmitting in 9-bit Data Mode16515.4 Break and Sync Transmit Sequence16515.5 Receiving in 8-bit or 9-bit Data Mode16515.6 Built-in IrDA Encoder and Decoder16515.7 Alternate UART I/O Pins165Register 15-1: U1MODE: UART1 MODE Register166Register 15-2: U1STA: UART1 Status and Control Register168TABLE 15-1: UART1 Register Map17016.0 10-bit 2 Msps Analog-to- Digital Converter (ADC) Module17116.1 Features17116.2 Description17116.3 Module Functionality171FIGURE 16-1: ADC Block Diagram172Register 16-1: A/D Control Register (ADCON)173Register 16-2: A/D Status Register (ADSTAT)175Register 16-3: A/D Base Register (ADBASE)176Register 16-4: A/D Port Configuration Register (ADPCFG)176Register 16-5: A/D Convert Pair Control Register #0 (ADCPC0)177Register 16-6: A/D Convert Pair Control Register #1 (ADCPC1)179Register 16-7: A/D Convert Pair Control Register #2 (ADCPC2)18116.4 ADC Result Buffer18316.5 Application Information183FIGURE 16-2: Application Example: Importance of Precise Sampling18316.6 Reverse Conversion Order18416.7 Simultaneous and Sequential Sampling in a pair18416.8 Group Interrupt Generation18416.9 Individual Pair Interrupts18516.10 Early Interrupt Generation18516.11 Conflict Resolution18516.12 Deliberate Conflicts18516.13 ADC Clock Selection18516.14 ADC Base Register185EXAMPLE 16-1: ADC Base Register Code186EXAMPLE 16-1: ADC Base Register Code (Continued)18716.15 Changing A/D Clock18716.16 Sample and Conversion18716.17 A/D Sample and Convert Timing188FIGURE 16-3: Detailed Conversion sequence timings, SEQSAMP = 0, not busy188FIGURE 16-4: Detailed Conversion sequence timings, SEQSAMP = 118916.18 Module Power-Down Modes19016.19 Effects of a Reset19016.20 Configuring Analog Port Pins19016.21 Output Formats190FIGURE 16-5: A/D Output Data Format191TABLE 16-1: ADC Register Map19217.0 SMPS Comparator Module19317.1 Features Overview193FIGURE 17-1: Comparator Module Block Diagram19317.2 Module Applications19317.3 Module Description19417.4 DAC19417.5 Interaction with I/O Buffers19417.6 Digital Logic19417.7 Comparator Input Range19417.8 DAC Output Range19417.9 Comparator Registers194Register 17-1: Comparator Control Registerx (CMPCONx)195Register 17-2: Comparator DAC Control Registerx (CMPDACx)196TABLE 17-1: Analog ComparAtor Control Register Map19718.0 System Integration19918.1 Oscillator System Overview19918.2 Oscillator Control Registers199FIGURE 18-1: OSCILLATOR SYSTEM BLOCK DIAGRAM200Register 18-1: OSCCON: Oscillator Control Register201Register 18-2: OSCTUN: Oscillator TUNING Register203Register 18-3: OSCTUN2: Oscillator Tuning Register 2204Register 18-4: LFSR: Linear Feedback Shift Register204Register 18-5: FOSCSEL: Oscillator Selection Configuration Bits205Register 18-6: FOSC: Oscillator Selection Configuration Bits20618.2.1 accidental write Protection20718.3 Oscillator Configurations207FIGURE 18-2: System Clock and Fadc Derivation20718.3.1 Initial Clock source selection208TABLE 18-1: Configuration Bit Values for Clock Selection20818.3.2 Oscillator Start-up Timer (OST)20818.3.3 Phase Locked Loop (PLL)208TABLE 18-2: PLL frequency range20818.4 PRIMARY oscillator on OSC1/ OSC2 pins:209FIGURE 18-3: Primary oscillator20918.5 External Clock Input209FIGURE 18-4: External Clock Input Operation (EC oscillator Configuration)209FIGURE 18-5: External Clock Input Operation (ECIO oscillator Configuration)20918.6 Internal Fast RC oscillator (FRC)21018.6.1 Frequency Range Selection21018.6.2 Nominal Frequency Values21018.6.3 FRC Frequency USER TUNING21018.6.4 Clock dithering logic21018.6.5 frequency sequencing mode21018.6.6 Pseudo random clock dithering mode21018.6.7 Fail-Safe Clock Monitor21018.7 Reset211FIGURE 18-6: FRC TUNE Dither Logic Block Diagram212FIGURE 18-7: Reset SYSTEM BLOCK DIAGRAM21218.7.1 POR: Power-ON reset213FIGURE 18-8: Time-out Sequence on Power-up (MCLR Tied to Vdd)213FIGURE 18-9: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1213FIGURE 18-10: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 221418.7.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled)21418.7.1.2 Operating without FSCM and PWRT214FIGURE 18-11: External Power-on Reset Circuit (for Slow Vdd Power-up)214TABLE 18-3: Initialization Condition for RCON RegisteR CASE 1215TABLE 18-4: Initialization Condition for RCON RegisteR CASE 221518.8 Watchdog Timer (WDT)21618.8.1 Watchdog Timer Operation21618.8.2 Enabling and Disabling the WDT21618.9 Power-Saving Modes21618.9.1 Sleep Mode21618.9.2 Idle Mode21718.10 Device Configuration Registers217TABLE 18-5: FGS and FBS Bit descriptions for the dsPIC30F1010218TABLE 18-6: FGS and FBS Bit Descriptions for the dsPIC30F202x218TABLE 18-7: FWDT and FPOR bit descriptions for dsPIC30F1010/202X21918.11 In-Circuit Debugger219TABLE 18-8: System Integration Register Map For dsPIC30F202x220TABLE 18-9: DEVICE Configuration Register Map22019.0 Instruction Set Summary221TABLE 19-1: Symbols used in Opcode Descriptions222TABLE 19-2: Instruction Set OVERVIEW 22420.0 Development Support22920.1 MPLAB Integrated Development Environment Software22920.2 MPASM Assembler23020.3 MPLAB C18 and MPLAB C30 C Compilers23020.4 MPLINK Object Linker/ MPLIB Object Librarian23020.5 MPLAB ASM30 Assembler, Linker and Librarian23020.6 MPLAB SIM Software Simulator23020.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator23120.8 MPLAB REAL ICE In-Circuit Emulator System23120.9 MPLAB ICD 2 In-Circuit Debugger23120.10 MPLAB PM3 Device Programmer23120.11 PICSTART Plus Development Programmer23220.12 PICkit 2 Development Programmer23220.13 Demonstration, Development and Evaluation Boards23221.0 Electrical Characteristics23321.1 DC Characteristics233TABLE 21-1: Operating MIPS vs. Voltage233TABLE 21-2: Thermal Operating Conditions234TABLE 21-3: Thermal Packaging Characteristics234TABLE 21-4: DC Temperature and Voltage specifications234TABLE 21-5: DC Characteristics: Operating Current (Idd) 235TABLE 21-6: DC Characteristics: Idle Current (iidle)237TABLE 21-7: DC Characteristics: Power-Down Current (Ipd)239TABLE 21-8: DC Characteristics: I/O Pin Input Specifications240TABLE 21-9: DC Characteristics: I/O Pin Output Specifications241TABLE 21-10: DC Characteristics: Program and EEPROM24121.2 AC Characteristics and Timing Parameters242TABLE 21-11: Temperature and Voltage Specifications – AC242FIGURE 21-1: Load Conditions for Device Timing Specifications242FIGURE 21-2: External Clock Timing242TABLE 21-12: External Clock Timing Requirements243TABLE 21-13: PLL Clock Timing Specifications (Vdd = 3.0 AND 5.0V)244TABLE 21-14: Internal Clock Timing examples244TABLE 21-15: AC Characteristics: Internal RC Accuracy245TABLE 21-16: AC Characteristics: Internal RC Jitter246FIGURE 21-3: CLKO and I/O Timing Characteristics247TABLE 21-17: CLKO and I/O Timing Requirements247FIGURE 21-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Character...248TABLE 21-18: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Timing Requirem...249FIGURE 21-5: band gap Start-up Time Characteristics250TABLE 21-19: band gap Start-up Time Requirements250FIGURE 21-6: Timer External Clock Timing Characteristics251TABLE 21-20: Timer1 External Clock Timing Requirements251TABLE 21-21: Timer2 External Clock Timing Requirements252TABLE 21-22: Timer3 External Clock Timing Requirements252FIGURE 21-7: INPUT CAPTURE (CAPx) TIMING Characteristics253TABLE 21-23: Input Capture timing requirements253FIGURE 21-8: Output Compare Module (OCx) Timing Characteristics253TABLE 21-24: Output Compare Module timing requirements253FIGURE 21-9: OC/PWM Module Timing Characteristics254TABLE 21-25: Simple OC/PWM MODE Timing Requirements254FIGURE 21-10: pOWER sUPPLY PWM Module fault Timing Characteristics255FIGURE 21-11: Power Supply PWM Module Timing Characteristics255TABLE 21-26: Power Supply PWM Module Timing Requirements255FIGURE 21-12: SPI Module Master Mode (CKE = 0) Timing Characteristics256TABLE 21-27: SPI Master mode (cke = 0) Timing requirements256FIGURE 21-13: SPI Module Master Mode (CKE =1) Timing Characteristics257TABLE 21-28: SPI Module Master mode (cke = 1) Timing requirements257FIGURE 21-14: SPI Module Slave Mode (CKE = 0) Timing Characteristics258TABLE 21-29: SPI Module Slave mode (cke = 0) Timing requirements258FIGURE 21-15: SPI Module Slave Mode (CKE = 1) Timing Characteristics259TABLE 21-30: SPI Module Slave mode (cke = 1) Timing requirements 260FIGURE 21-16: I2C™ Bus Start/Stop Bits Timing Characteristics (Master mode)261FIGURE 21-17: I2C™ Bus Data Timing Characteristics (Master mode)261TABLE 21-31: I2C™ Bus Data Timing Requirements (Master Mode)262FIGURE 21-18: I2C™ Bus Start/Stop Bits Timing Characteristics (slave mode)263FIGURE 21-19: I2C™ Bus Data Timing Characteristics (slave mode)263TABLE 21-32: I2C™ Bus Data Timing Requirements (Slave Mode)264TABLE 21-33: 10-bit High-speed a/d Module Specifications265FIGURE 21-20: A/d Conversion Timing Per Input266TABLE 21-34: Comparator Operating Conditions267TABLE 21-35: comparator AC AND DC Specifications267TABLE 21-36: DAC DC Specifications267TABLE 21-37: DAC AC Specifications26722.0 Package Marking Information269Appendix A: Revision History277INDEX279Worldwide Sales and Service286Dimensioni: 3,97 MBPagine: 286Language: EnglishApri il manuale
