Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
Motor Controller (MC10B8CV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
673
20.3.2
Register Descriptions
20.3.2.1
Motor Controller Control Register 0
This register controls the operating mode of the motor controller module.
0x003E
Reserved
—
0x003F
Reserved
—
1
Write accesses to “Reserved” addresses have no effect. Read accesses to “Reserved” addresses provide
invalid data (0x0000).
invalid data (0x0000).
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R
0
MCPRE[1:0]
MCSWAI
FAST
DITH
0
MCTOIF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-3. Motor Controller Control Register 0 (MCCTL0)
Table 20-3. MCCTL0 Field Descriptions
Field
Description
6:5
MCPRE[1:0]
Motor Controller Prescaler Select — MCPRE1 and MCPRE0 determine the prescaler value that sets the
motor controller timer counter clock frequency (f
TC
). The clock source for the prescaler is the peripheral bus
clock (f
BUS
) as shown in
. Writes to MCPRE1 or MCPRE0 will not affect the timer counter clock
frequency f
TC
until the start of the next PWM period.
shows the prescaler values that result from
the possible combinations of MCPRE1 and MCPRE0
4
MCSWAI
Motor Controller Module Stop in Wait Mode
0 Entering wait mode has no effect on the motor controller module and the associated port pins maintain the
0 Entering wait mode has no effect on the motor controller module and the associated port pins maintain the
functionality they had prior to entering wait mode both during wait mode and after exiting wait mode.
1 Entering wait mode will stop the clock of the module and debias the analog circuitry. The
module will release the pins.
3
FAST
Motor Controller PWM Resolution Mode
0 PWM operates in 11-bit resolution mode, duty cycle registers of all channels are switched to word mode.
1 PWM operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode.
1 PWM operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode.
2
DITH
Motor Control/Driver Dither Feature Enable (refer to
)
0 Dither feature is disabled.
1 Dither feature is enabled.
1 Dither feature is enabled.
0
MCTOIF
Motor Controller Timer Counter Overflow Interrupt Flag — This bit is set when a motor controller timer
counter overflow occurs. The bit is cleared by writing a 1 to the bit.
0 A motor controller timer counter overflow has not occurred since the last reset or since the bit was cleared.
1 A motor controller timer counter overflow has occurred.
1 A motor controller timer counter overflow has occurred.
Figure 20-2. MC10B8C Memory Map (continued)
Offset
Register
Access