Analog Devices AD9609 Evaluation Board AD9609-65EBZ AD9609-65EBZ Scheda Tecnica
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AD9609-65EBZ
AD9609
Rev. 0 | Page 21 of 32
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9609 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without
affecting the performance of the AD9609. Noise and distortion
performance are nearly flat for a wide range of duty cycles with
the DCS on, as shown in Figure 51.
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without
affecting the performance of the AD9609. Noise and distortion
performance are nearly flat for a wide range of duty cycles with
the DCS on, as shown in Figure 51.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
80
75
70
65
60
55
50
40
45
10
20
30
40
50
60
70
80
POSITIVE DUTY CYCLE (%)
SN
R
(
d
B
F
S
)
08
54
1-
0
53
DCS ON
DCS OFF
Figure 51. SNR vs. DCS On/Off
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNR
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNR
LF
) at a given input frequency (f
INPUT
) due to
jitter (t
JRMS
) can be calculated by
SNR
HF
= −10 log[(2π × f
INPUT
× t
JRMS
)
2
+ 10
]
)
10
/
(
LF
SNR
−
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
NR (
d
BF
S
)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
2.5ps
3.0ps
0
854
1-
0
22
Figure 52. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal when
aperture jitter may affect the dynamic range of the AD9609. To
avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
aperture jitter may affect the dynamic range of the AD9609. To
avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
For more information, see the AN-501 Application Note and
the AN-756 Application Note available at
the AN-756 Application Note available at