Analog Devices AD9609 Evaluation Board AD9609-65EBZ AD9609-65EBZ Scheda Tecnica
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AD9609-65EBZ
AD9609
Rev. 0 | Page 23 of 32
TIMING
The AD9609 provides latched data with a pipeline delay of
eight clock cycles. Data outputs are available one propagation
delay (t
eight clock cycles. Data outputs are available one propagation
delay (t
PD
) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9609. These
transients can degrade converter dynamic performance.
on them to reduce transients within the AD9609. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9609 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance can degrade.
clock rates below 3 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9609 provides a data clock output (DCO) signal
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 for a
graphical timing description.
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 for a
graphical timing description.
Table 13. Output Data Format
Input (V)
Condition (V)
Offset Binary Output Mode
Twos Complement Mode
OR
VIN+ − VIN−
< −VREF − 0.5 LSB
00 0000 0000
10 0000 0000
1
VIN+ − VIN−
= −VREF
00 0000 0000
10 0000 0000
0
VIN+ − VIN−
= 0
10 0000 0000
00 0000 0000
0
VIN+ − VIN−
= +VREF − 1.0 LSB
11 1111 1111
01 1111 1111
0
VIN+ − VIN−
> +VREF − 0.5 LSB
11 1111 1111
01 1111 1111
1