Analog Devices AD9609 Evaluation Board AD9609-65EBZ AD9609-65EBZ Scheda Tecnica
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AD9609-65EBZ
AD9609
Rev. 0 | Page 6 of 32
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
cycle clock, DCS disabled, unless otherwise noted.
Table 3.
Parameter Temp
AD9609-20/AD9609-40/AD9609-65/AD9609-80
Unit
Min Typ
Max
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Internal Common-Mode Bias
Full
0.9
V
Differential Input Voltage
Full
0.2
3.6
V p-p
Input Voltage Range
Full
GND − 0.3
AVDD + 0.2
V
High Level Input Current
Full
−10
+10
μA
Low Level Input Current
Full
−10
+10
μA
Input Resistance
Full
8
10
12
kΩ
Input Capacitance
Full
4
pF
LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)
High Level Input Voltage
Full
1.2
DRVDD + 0.3
V
Low Level Input Voltage
Full
0
0.8
V
High Level Input Current
Full
−50
−75
μA
Low Level Input Current
Full
−10
+10
μA
Input Resistance
Full
30
kΩ
Input Capacitance
Full
2
pF
LOGIC INPUTS (CSB)
High Level Input Voltage
Full
1.2
DRVDD + 0.3
V
Low Level Input Voltage
Full
0
0.8
V
High Level Input Current
Full
−10
+10
μA
Low Level Input Current
Full
40
135
μA
Input Resistance
Full
26
kΩ
Input Capacitance
Full
2
pF
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, I
OH
= 50 μA
Full
3.29
V
High Level Output Voltage, I
OH
= 0.5 mA
Full
3.25
V
Low Level Output Voltage, I
OL
= 1.6 mA
Full
0.2
V
Low Level Output Voltage, I
OL
= 50 μA
Full
0.05
V
DRVDD = 1.8 V
High Level Output Voltage, I
OH
= 50 μA
Full
1.79
V
High Level Output Voltage, I
OH
= 0.5 mA
Full
1.75
V
Low Level Output Voltage, I
OL
= 1.6 mA
Full
0.2
V
Low Level Output Voltage, I
OL
= 50 μA
Full
0.05
V
1
Internal 30 kΩ pull-down.
2
Internal 30 kΩ pull-up.