Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Scheda Tecnica

32099G–06/2011

The duty cycle registers will be corrupted if written when the timebase counter overflows. If
the duty cycle registers are written exactly when the timebase counter overflows at TOP, the
duty cycle registers may become corrupted.
Fix/Workaround
Write to the duty cycle registers only directly after the Timebase Overflow bit in the status
register is set.

Open Drain mode does not work
The open drain mode does not work.
Fix/Workaround
None.

BUSY bit is never cleared after writes to the Control Register (CR)
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN == 0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.

Incoming peripheral events are discarded during duty cycle register update
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA period
when an incoming peripheral event is expected.

VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.

When the main clock is RCSYS, TIMER_CLOCK5 is equal to CLK_PBA
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to CLK_PBA and
not CLK_PBA/128. 
Fix/Workaround
None.

Pendetect in sleep modes without CLK_ADCIFB will not wake the system
The pendetect will not wake the system from a sleep mode if the clock for the ADCIFB
(CLK_ADCIFB) is turned off.
Fix/Workaround
Use a sleep mode where CLK_ADCIFB is not turned off to wake the part using pendetect. 

8-bit mode is not working
Do not use the ADCIFB 8-bit mode.
Fix/Workaround
Use the 10-bit mode and shift right by two bits.