Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Scheda Tecnica

32099G–06/2011

Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST). 

SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0. 

SPI mode fault detection enable causes incorrect behavior
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.

SPI RDR.PCS is not correct
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not
correctly indicate the value on the NPCS pins at the end of a transfer.
Fix/Workaround
Do not use the PCS field of the SPI RDR. 

TWI pins are not SMBus compliant
The TWI pins draw current when they are supplied with 3.3V and the part is left unpowered.
Fix/Workaround
None.

PA21, PB04, and PB05 are not 5V tolerant
Pins PA21, PB04, and PB05 are only 3.3V tolerant.
Fix/Workaround
None.

PB04 SMBALERT function should not be used
The SMBALERT function from TWIMS0 should not be selected on pin PB04.
Fix/Workaround
None.

TWIM STOP bit in IMR always reads as zero
The STOP bit in IMR always reads as zero.
Fix/Workaround
None.

Disabled TWIM drives TWD and TWCK low
When the TWIM is disabled, it drives the TWD and TWCK signals with logic level zero. This
can lead to communication problems with other devices on the TWI bus.
Fix/Workaround