Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
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AT91SAM9N12-EK
453
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
31.7.7 DDRSDRC
Low-power
Register
Name:
DDRSDRC_LPR
Address:
0xFFFFE81C
Access:
Read-write
Reset:
See
• LPCB: Low-power Command Bit
Reset value is 0.
• CLK_FR: Clock Frozen Command Bit
Reset value is “0”.
This field sets the clock low during power-down mode or during deep power-down mode. Some SDRAM devices do not support
freezing the clock during power-down mode or during deep power-down mode. Refer to the SDRAM device datasheet for details
on this.
freezing the clock during power-down mode or during deep power-down mode. Refer to the SDRAM device datasheet for details
on this.
0: Clock(s) is/are not frozen.
1: Clock(s) is/are frozen.
• PASR: Partial Array Self Refresh
Reset value is “0”.
This field is unique to Low-power SDRAM. It is used to specify whether only one quarter, one half or all banks of the SDRAM
array are enabled. Disabled banks are not refreshed in self-refresh mode.
array are enabled. Disabled banks are not refreshed in self-refresh mode.
The values of this field are dependant on Low-power SDRAM devices.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
UPD_MR
–
–
–
APDE
15
14
13
12
11
10
9
8
–
–
TIMEOUT
–
DS
7
6
5
4
3
2
1
0
–
PASR
CLK_FR
LPCB
Value
Name Description
0
NOLOWPOWER
Low-power feature is inhibited: no power-down, self-refresh and deep power mode are
issued to the SDRAM device.
issued to the SDRAM device.
1
SELFREFRESH
The DDRSDRC issues a Self Refresh Command to the SDRAM device, the clock(s)
is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self-
refresh mode when accessed and enters it after the access.
is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self-
refresh mode when accessed and enters it after the access.
2
POWERDOWN
The DDRSDRC issues a Power-down Command to the SDRAM device after each
access, the CKE signal is set low. The SDRAM device leaves the power-down
mode when accessed and enters it after the access.
access, the CKE signal is set low. The SDRAM device leaves the power-down
mode when accessed and enters it after the access.
3
DEEPPOWERDOWN
The DDRSDRC issues a Deep Power-down Command to the Low-power SDRAM
device.
device.
Note:
This mode is unique to Low-power SDRAM devices.