Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica

454

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

After the initialization sequence, as soon as PASR field is modified, Extended Mode Register in the external device memory is 
accessed automatically and PASR bits are updated. In function of the UPD_MR bit, update is done before entering in self-refresh 
mode or during a refresh command and a pending read or write access.

Reset value is “0”.

Note:

This field is unique to Low-power SDRAM.

It selects the driver strength of SDRAM output (see memory devices datasheet for details).

After the initialization sequence, as soon as DS field is modified, Extended Mode Register is accessed automatically and DS bits 
are updated. In function of UPD_MR bit, update is done before entering in self-refresh mode or during a refresh command and a 
pending read or write access.

Reset value is “0”. This field defines when low-power mode is enabled.

Reset value is “1”.

Note:

This mode is unique to DDR2-SDRAM devices. 

This mode allows to determine the active power-down mode, which determines performance versus power saving.

After the initialization sequence, as soon as APDE field is modified, Extended Mode Register (located in the memory of the exter-
nal device) is accessed automatically and APDE bits are updated. In function of the UPD_MR bit, update is done before entering 
in self-refresh mode or during a refresh command and a pending read or write access

Reset value is “0”. 

This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This update is 
function of DDRSDRC integration in a system. DDRSDRC can either share or not, an external bus with another controller.

0

NONE

SDRAM low-power mode is activated immediately after the end of the last transfer.

1

CLK64

SDRAM low-power mode is activated 64 clock cycles after the end of the last transfer.

2

CLK128

SDRAM low-power mode is activated 128 clock cycles after the end of the last transfer.

0

DDR2_FAST_EXIT

Fast Exit from Power Down. DDR2-SDRAM devices only. 

1

DDR2_SLOW_EXIT

Slow Exit from Power Down. DDR2-SDRAM devices only.

0

NO_UPDATE

Update is disabled.

1

UPDATE_SHAREDBUS

DDRSDRC shares external bus. Automatic update is done during a refresh command and 
a pending read or write access in SDRAM device.

2

UPDATE_NOSHAREDBUS

DDRSDRC does not share external bus. Automatic update is done before entering in self-
refresh mode.