Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica
Codici prodotto
ATSAMD20-XPRO
284
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
consumption. Input value can always be read, whether the pin is configured as input or output, except if digital input is
disabled by writing a zero to the INEN bit in the Pin Configuration registers (PINCFGy).
disabled by writing a zero to the INEN bit in the Pin Configuration registers (PINCFGy).
The PORT also allows peripheral functions to be connected to individual I/O pins by writing a one to the corresponding
PMUXEN bit in the PINCFGy registers and by writing the chosen selection to the Peripheral Multiplexing registers
(PMUXn - refer to
PMUXEN bit in the PINCFGy registers and by writing the chosen selection to the Peripheral Multiplexing registers
(PMUXn - refer to
) for that pin. This will override the connection between the PORT and that I/O pin, and connect
the selected peripheral line bundle to the pad instead of the PORT line bundle.
Each group of up to 32 pins is controlled by a set of registers, as described in
duplicated for each group of pins, with increasing base addresses.
Figure 21-3. Overview of the Peripheral Functions Multiplexing
21.6.2 Basic Operation
21.6.2.1 Initialization
After reset, all standard-function device I/O pads are connected to the PORT with outputs tri-stated and input buffers
disabled, even if no clocks are running. Specific pins, such as the ones used for connection to a debugger, may be
configured differently, as required by their special function.
disabled, even if no clocks are running. Specific pins, such as the ones used for connection to a debugger, may be
configured differently, as required by their special function.
21.6.3 Basic Operation
Each I/O pin y can be configured and accessed by reading or writing PORT registers. Because PORT registers are
grouped into sets of registers for each group of up to 32 pins, the base address of the register set for pin y is at byte
address PORT + (y / 32) * 0x80. (y / 32) will be used as the index within that register set.
grouped into sets of registers for each group of up to 32 pins, the base address of the register set for pin y is at byte
address PORT + (y / 32) * 0x80. (y / 32) will be used as the index within that register set.
To use pin y as an output, configure it as output by writing the (y / 32) bit in the DIR register to one. To avoid disturbing
the configuration of other pins in that group, this can also be done by writing the (y / 32) bit in the DIRSET register to one.
The desired output value can be set by writing the (y / 32) bit to that value in register OUT.
the configuration of other pins in that group, this can also be done by writing the (y / 32) bit in the DIRSET register to one.
The desired output value can be set by writing the (y / 32) bit to that value in register OUT.
Similarly, writing an OUTSET bit to one will set the corresponding bit in the OUT register to one, while writing an
OUTCLR bit to one will set it to zero, and writing an OUTTGL bit to one will toggle that bit in OUT.
OUTCLR bit to one will set it to zero, and writing an OUTTGL bit to one will toggle that bit in OUT.
To use pin y as an input, configure it as input by writing the (y / 32) bit in the DIR register to zero. To avoid disturbing the
configuration of other pins in that group, this can also be done by writing the (y / 32) bit in DIRCLR register to one. The
configuration of other pins in that group, this can also be done by writing the (y / 32) bit in DIRCLR register to one. The
Port y PINCFG
Port y
Periph Line 0
PORT bit y
PMUXEN
Data+Config
Periph Line 1
Periph Line 15
Port y
PMUX[3:0]
Port y PMUX Select
PORTMUX
Port y Line Bundle
PAD y
Pad y
Peripheral Line Bundles
to be muxed to Pad y
to be muxed to Pad y
Port y Peripheral
Mux Enable
Mux Enable
15
1
0
0
1
Line Bundle